US 6,606,724 B1Granted

Method and apparatus for decoding of a serially concatenated block and convolutional code

AssigneeConexant Systems, Inc.

InventorsAbraham Krieger, Donald Brian Eidson

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Abstract

A decoder having a first decoder providing first decoded data. A deinterleaver is included for deinterleaving the first decoded data. A second decoder provides second decoded data based on the deinterleaved first decoded data. The second decoder provides at least one decode status signal indicative of second decoder operations. A pipeline decoder unit is included that is coupled to the second decoder. The pipeline decoder unit includes an encoder that receives the second decoded data and provides forced decision data, a multiplexer, and a third decoder that provides pipelined decoded data. The multiplexer is responsive to the at least one decode status signal to selectively constrain the pipelined decoded data to be at least partially dependent on the forced decision data.

Claims31

Dependent claims

A decoding system for decoding serially concatenated encoded symbols comprising:

a first serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the first serial concatenated code decoder configured to receive as an input data derived from the serially concatenated encoded symbols, and the hard input outer decoder of the first serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators;
and
a first replicable unit comprising:
a first interleaver, an inner encoder, and a mapper coupled in series, wherein the first interleaver is configured to interleave data derived from the hard bit decisions, and the mapper is configured to map encoded information from the inner encoder into high-reliability soft values;
a second interleaver and a modified inner encoder coupled in series, wherein the second interleaver is configured to interleave data derived from the status indicators, and the modified inner encoder is configured to produce selection values;
a multiplexor for selecting, responsive to the selection values, between outputting data derived from the serially concatenated encoded symbols as delayed and the high reliability soft values;
and
a second serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the second serial concatenated code decoder configured to receive as an input data derived from the output of the multiplexor, and the hard input outer decoder of the second serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators.

5 more elements

A decoding system for decoding serially concatenated encoded symbols comprising:

a first serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the first serial concatenated code decoder configured to receive as an input data derived from the serially concatenated encoded symbols, and the hard input outer decoder of the first concatenated code decoder configured to output hard bit decisions and corresponding status indicators;
and
a first replicable unit comprising:
a first interleaver configured to interleave data derived from the hard bit decisions;
a second interleaver configured to interleave data derived from the status indicators;
and
a second serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the second serial concatenated code decoder configured to (1) receive as inputs data derived from the interleaved status indicators and interleaved hard bit decisions, and data derived from the serial concatenated encoded symbols as delayed, and (2) selectively render state or branch metrics as undesirable responsive to the data derived from the interleaved status indicators, and the hard input outer decoder of the second serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators.

4 more elements

A decoding system for decoding serially concatenated encoded symbols comprising:

first serial concatenated code decoding means for receiving as an input data derived from the serially concatenated encoded symbols, and outputting bard bit decisions and corresponding status indicators;
and
a first replicable unit comprising:
first interleaving means for interleaving data derived from the hard bit decisions;
second interleaving means for interleaving data derived from the status indicators;
and
second serial concatenated code decoding means for outputting hard bit decisions and corresponding us indicators responsive to the interleaved data from the first and second interleaving means.

4 more elements

A method of decoding serially concatenated encoded symbols comprising:

outputting hard bit decisions and corresponding status indicators responsive to data derived from the serially concatenated encoded symbols;
and
performing the following substeps in a first replicable unit:
interleaving data derived from the hard bit decisions;
interleaving data derived from the status indicators;
and
outputting hard bit decisions and corresponding status indicators responsive to data derived from the interleaved status indicators, the interleaved hard bit decisions, and the serial concatenated encoded symbols as delayed.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/492,962Filed 28 Jan 2000
Granted: 12 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03M 13/2972
Particular turbo code structure: serial concatenation using convolutional component codes
H03M 13/09
Using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits: error detection only, e.g.…
H03M 13/15
Linear codes: cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial,…
H03M 13/2936
Using a block and a convolutional code: comprising an outer Reed-Solomon code and an inner convolutional code