Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level

An apparatus for automatically detecting a signaling level comprising:

• an input for a first signal, said first signal to have a voltage potential to be evaluated, said first signal having information about an external signaling level;
• an input for a second signal, said second signal to have a reference voltage;
• an evaluation device coupled to said first input and said second input, said evaluation device to determine whether said first signal has a higher voltage potential than said reference voltage and to generate a result, said determination to occur upon receipt of an indication that said first signal has achieved an acceptable level;
• a latch coupled to said evaluation device, said latch to store said result from said evaluation device, said result to indicate whether said external signaling level is at a first signaling voltage or a second signaling voltage, wherein said first signaling voltage is higher than said second signaling voltage;
• and
• an output coupled to said latch, said output to drive a signal indicating said result to a buffer, said buffer configurable to operate at said external signaling level, said signal further to configure said buffer to a default signaling voltage equal to said first signaling voltage prior to latching of said result from said determination.

A method of automatically detecting a signaling level comprising:

• receiving a first signal into a circuit for evaluation, wherein said first signal is encoded to indicate an external input/output (I/O) signaling level;
• generating a second signal from said first signal by passing said first signal through a voltage divider to reduce said first signal to a lower voltage potential;
• evaluating said second signal relative to a third signal to determine whether said second signal has a higher voltage potential than said third signal and generating a result, said evaluation to occur upon receipt of an indication that said first signal is valid;
• latching said result of said evaluation in response to a clock signal and receipt of said indication, said result to indicate whether said external input/output signaling level is at a first signaling voltage or a second signaling voltage, wherein said first signaling voltage is greater than said second signaling voltage;
• outputting said result from said circuit;
• and
• configuring an I/O buffer to operate with said external I/O signal level based said on result, said I/O buffer initialized to operate at a default signaling level prior to said latching of said result from said evaluation, said default signaling level having a voltage level of at least said first signaling voltage.

An apparatus for automatically detecting a signaling level comprising:

• an input for a first signal, said first signal to have a voltage potential to be evaluated, said voltage potential to indicate an external input/output (I/O) signaling level;
• a voltage divider coupled to said input and to receive said first signal, said voltage divider to generate a second signal having a lower voltage potential than said first signal;
• an evaluation device coupled to said voltage divider, said evaluation device to determine whether said second signal has a higher voltage potential than a reference voltage and to generate a result, said determination to occur after receipt of an indication that said first signal is at least a requisite level;
• a latch coupled to said evaluation device, said latch to store said result from said evaluation device, said result to indicate whether said external signaling level is at a first signaling level or a second signaling level, wherein said first signaling level is higher than said second signaling level;
• and
• an output coupled to said latch, said output to drive a signal indicating said result to a buffer configurable to operate with said external I/O signaling level, said signal to initially configure said buffer to a default signaling level prior to latching of said result from said determination, and said signal further to configure said buffer to said external I/O signaling level after said latching.

A memory controller hub comprising:

• a bus master and a bus bridge;
• a memory control logic coupled to said bus master;
• a system control logic coupled to said memory control logic;
• an Accelerated Graphics Port (AGP) interconnect coupled to said memory control logic;
• and
• a voltage detector circuit coupled to said Accelerated Graphics Port interconnect, said voltage detector circuit comprising
• an input to receive a first signal from said AGP interconnect, said first signal to have a voltage potential to be evaluated, said voltage potential to indicate an input/output (I/O) signaling level of said AGP interconnect;
• an evaluation device coupled to said input, said evaluation device to determine whether said first signal has a higher voltage potential than a reference voltage and to generate a result, said determination to occur after receipt of an indication that said first signal is at least a requisite level;
• a latch coupled to said evaluation device, said latch to store said result from said evaluation device, said result to indicate whether said I/O signaling level of said AGP interconnect is at a first signaling level or a second signaling level, wherein said first signaling level is higher than said second signaling level;
• and
• an output coupled to said latch, said output to drive a signal indicating said result, said output for configuring characteristics of buffers to operate with said I/O signaling level on said AGP interconnect, said signal to initially configure said buffers to a default signaling level prior to latching of said result from said determination, and said signal further to configure said buffers at said I/O signaling level of said AGP interconnect after said latching.

A digital processing system comprising:

• a processor;
• a main memory coupled to said processor;
• a memory controller hub coupled to said processor, said memory controller hub having an Accelerated Graphics Port without a type detection pin, said memory controller hub having a voltage detector for detecting a signaling level of a device coupled to said Accelerated Graphics Port and internal logic for programming buffer characteristics, said memory controller hub comprising:
• an evaluation device to determine whether said first signal from said Accelerate Graphics Port has a higher voltage potential than a reference voltage and to generate a result for said determination after receipt of an indication that said first signal is at least a requisite level;
• said result to indicate whether said signaling level of said device is at a first signaling voltage or a second signaling voltage, wherein said first signaling voltage is higher than said second signaling voltage;
• and
• an output to drive a control signal for configuring characteristics of input/output buffers to operate with said signaling level of said device, said signal to initially configure said buffers to a default signaling level prior to generation of said result, and said signal further to configure said buffers at said signaling level of said device after said determination;
• and
• a video card coupled to said Accelerated Graphics Port.