Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
AssigneeIntel Corporation
InventorsMatthew J. Adiletta, Gilbert Wolrich, William Wheeler
Life of this patent
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
Claims17
A parallel hardware-based multithreaded processor comprises:
- a plurality of microengines that support multiple hardware threads, each microengine comprising:
- a plurality of program counters;
- with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time;
- a general purpose processor that coordinates system functions, the general purpose processor loading microcontrol programs for the plurality of microcontrol engines;
- and
- a first bus to couple the general purpose processor to the plurality of microengines.
A parallel hardware-based multithreaded processor comprises:
- a plurality of microengines that support multiple hardware threads, each microengine comprising:
- a plurality of program counters;
- with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time;
- a general purpose processor that coordinates system functions, the general purpose processor loading microcontrol programs for the plurality of microcontrol engines;
- a media access controller device coupled to an interface;
- and
- a first bus to couple the general purpose processor, the plurality of microengines, and the interface.
A parallel hardware-based multithreaded processor comprises:
- a general purpose processor that coordinates system functions;
- and
- a plurality of microengines that support multiple hardware threads, the microengines comprising:
- a control store to store a microprogram;
- the microprogram loadable by the general purpose processor;
- controller logic including an instruction decoder and program counter unit to execute the microprogram;
- and
- a plurality of program counters;
- with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time.
Dependencies are inferred from the claim text.