Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions

A processor which decodes and executes an instruction sequence, the processor including:

• an obtaining means for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor,
• wherein the instruction set is assigned at least one first conditional flag setting instruction, at least one second conditional flag setting instruction, and at least one conditional execution instruction,
• each first conditional flag setting instruction including a first condition, and each second conditional flag setting instruction including a second condition, each first condition being mutually exclusive with one of the second conditions,
• each conditional execution instruction including an operation code that is not included in any other conditional execution instruction in the instruction set;
• a decoding means for decoding each instruction in the obtained instruction sequence one by one;
• a conditional flag for holding a judgement result as to whether a predetermined condition is satisfied;
• a judging means for judging, when the decoding means decodes the first conditional flag setting instruction, whether the first condition in the first conditional flag setting instruction is satisfied and has the conditional flag hold a judgement result for the first condition and, when the decoding means decodes the second conditional flag setting instruction, judges whether the second condition in the second conditional flag setting instruction is satisfied and has the conditional flag hold a judgement result for the second condition;
• and
• an execution means for executing, only if the decoding means decodes the conditional execution instruction and the judgement result held by the conditional flag indicates that a condition for the conditional execution instruction is satisfied, an operation specified by the operation code in the conditional execution instruction.

A processor which decodes and executes an instruction sequence, the processor comprising:

• a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction;
• an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor,
• wherein the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second stake condition specifying either of one state and a plurality of states;
• a decoding unit for decoding each instruction in the obtained instruction sequence one by one;
• a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction;
• and
• an execution unit for executing an operation specified by the operation code in the second conditional instruction, and subsequently, only if a judgment result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

A processor which decodes and executes an instruction sequence, the processor including:

• an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor,
• wherein the instruction set is assigned at least one first conditional flag setting instruction, at least one second conditional flag setting instruction, and at least one conditional execution instruction,
• each first conditional flag setting instruction including a first condition, and each second conditional flag setting instruction including a second condition, each first condition being mutually exclusive with one of the second conditions,
• each conditional execution instruction including an operation code that is not included in any other conditional execution instruction in the instruction set;
• a decoding unit for decoding each instruction in the obtained instruction sequence one by one;
• a conditional flag for holding a judgment result as to whether a predetermined condition is satisfied;
• a judging unit for judging, when the decoding unit decodes the first conditional flag setting instruction, whether the first condition in the first conditional flag setting instruction is satisfied and has the conditional flag hold a judgment result for the first condition and, when the decoding unit decodes the second conditional flag setting instruction, judges whether the second condition in the second conditional flag setting instruction is satisfied and has the conditional flag hold a judgment result for the second condition;
• and
• an execution unit for executing an operation specified by an operation code that is not included in any conditional execution instruction in the instruction set, and subsequently, only if the decoding unit decodes the conditional execution instruction and the judgment result held by the conditional flag indicates that a condition for the conditional execution instruction is satisfied, an operation specified by the operation code in the conditional execution instruction.