Multiprocessor speculation mechanism with imprecise recycling of storage operations

A data processing system comprising:

• a memory system;
• a plurality of processors coupled to an interconnect, wherein at least one of said plurality of processors includes:
• an instruction sequencing unit for fetching an instruction sequence for execution in program order, said instruction sequence including a barrier instruction and a load instruction that follows said barrier instruction;
• a load/store unit (LSU) including a controller that speculatively issues a load request to said memory system in response to said load instruction while a barrier operation associated with said barrier instruction is pending;
• and
• means, responsive to a pre-determined type of invalidate with respect to said speculatively issued load request, for discarding data returned by said load request and re-issuing said load request.

A method of operating a processor, said method comprising the steps of:

• receiving an instruction sequence for execution, said instruction sequence including a barrier instruction and a load instruction that follows said barrier instruction in program order;
• in response to said barrier instruction, issuing a barrier operation on an interconnect;
• in response to said load instruction and while said barrier operation is pending, speculatively issuing a load request to memory;
• and
• in response to a pre-determined type of invalidate with respect to said speculatively issued load request, discarding data returned by memory in response to said load request and re-issuing said load request.