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US 6,606,700 B1Granted
DSP with dual-mac processor and dual-mac coprocessor
AssigneeQUALCOMM Incorporated
InventorsGilbert C. Sih, Hemant Kumar, Way-Shing Lee
Life of this patent
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Abstract
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.
Claims6
An electronic circuit, characterized in that it includes:
- (a) a register file having first through third inputs and first through sixth outputs;
- (b) a first shifter receiving the first output of the register file;
- (c) a first multiplier receiving the second and third outputs of the register file and having an output;
- (d) a second multiplier receiving the fourth and fifth outputs of the register file and having an output;
- (e) a second shifter receiving the output of the first multiplier and having an output;
- (f) a third shifter receiving the output of the second multiplier and having an output;
- (g) a rounding multiplexer receiving the output of the first shifter and having an output;
- (h) a first adder receiving, at a first input, the output of the second shifter and having an output;
- (i) a first externally-controlled multiplexer receiving either a zero or the output of the third shifter, and applying an output to a second input of the first adder;
- (j) a second adder receiving the outputs of the rounding multiplexer and the first adder, and having an output which is fed back to the first input of the register file;
- (k) a third adder receiving the outputs of the third shifter and the sixth register output, and having an output which is fed back to the second input of the register file;
- (l) a first input storage element receiving the third output of the register file;
- (m) a second externally-controlled multiplexer receiving the output of the first input storage element, and the third output of the register file;
- (n) a third externally-controlled multiplexer receiving the second and fifth outputs of the register file;
- (o) a third multiplier receiving the outputs of the second and third externally-controlled multiplexers;
- (p) a fourth shifter receiving the output of the third multiplier;
- (q) a fourth adder receiving, at a first input, the output of the fourth shifter;
- (r) a first output storage element receiving the output of the fourth adder, the output of the first output storage element being applied to a second input of the fourth adder;
- (s) a fourth externally-controlled multiplexer receiving the output of the first input storage element and the fourth output of the register file;
- (t) a second input storage element receiving the output of the fourth externally-controlled multiplexer;
- (u) a fifth externally-controlled multiplexer receiving the output of the second input storage element and the fourth output of the register file;
- (v) a fourth multiplier receiving the output of the fifth externally-controlled multiplexer and the second output of the register file;
- (w) a fifth shifter receiving the output of the fourth multiplier;
- (x) a fifth adder receiving, at a first input, the output of the fifth shifter;
- (y) a second output storage element receiving the output of the fifth adder, the output of the first output storage element being applied to a first input of a sixth externally-controlled multiplexer, the sixth externally-controlled multiplexer, receiving the output of the fourth shifter at a second input, and the output of the sixth externally-controlled multiplexer being applied to a second input of the fifth adder.
22 more elements
An electronic circuit wherein:
- (a) the electronic circuit includes a register file including at least one input and at least four outputs;
- and
- (b) the electronic circuit is characterized in that is further includes:
- (1) first, second, third, and fourth multipliers, each having at least two inputs;
- (2) first, second, third, and fourth adders, each adder having as a first input an output of the corresponding multiplier;
- (3) means for associating the outputs of the register file with the inputs of at least some of the multipliers;
- (4) means for associating another input of at least some of the adders with an output of another multiplier, or with an output of the register file;
- and
- (5) at least one input storage element:
- (a) whose input is connected to:
- (1) an output of the register file:
- or
- (2) an output of another input storage element;
- and
- (b) whose output is connected to:
- (1) an input of at least one of the multipliers:
- or
- an input of another input storage element;
- whereby the multipliers, adders, input storage elements and register file operate, together, in a single clock cycle.
16 more elements
An electronic circuit wherein:
- the electronic circuit includes a register file including at least one input and at least four outputs:
- and
- the electronic circuit is characterized in that is further includes:
- first, second, third, and fourth multipliers, each having at least two inputs;
- first, second, third, and fourth adders, each adder having as a first input an output of the corresponding multiplier;
- means for associating the outputs of the register file with the inputs of at least some of the multipliers;
- means for associating another input of at least some of the adders with an output of another multiplier, or with an output of the register file;
- and
- at least one output storage element, connected to an output of at least one of the adders, whereby the multipliers, adders, output storage elements, and register file operate, together, in a single clock cycle.
6 more elements
Dependencies are inferred from the claim text.