US 6,606,699 B2Granted

Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit

AssigneeBOPS, Inc.

InventorsGerald G. Pechanek, Juan G. Revilla

Life of this patent

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Abstract

An apparatus for concurrently executing controller single instruction single data (SISD) instructions and single instruction multiple data (SIMD) processing element instructions comprising a combined controller and processing element. At least first and second simplex instructions each comprise a mode of operation bit, said mode of operation bit in the first simplex instruction specifying a controller SISD operation for execution by the controller, and the mode of operation bit in the second simplex instruction specifying a procesing element SIMD operation for execution by the processsing element. A very long instruction word (VLIW) contains said at least first and second simplex instructions.

Claims3

Dependent claims

A method operating a merged processor including a control processor and a processing element, the method comprising the steps of:

(a) fetching a very long instruction word (VLIW) by the merged processor, the VLIW comprising:
(i) a first simplex instruction including a mode of operation bit defining the first simplex instruction as a control processor instruction, and
(ii) a second simplex instruction including a mode of operation bit defining the second simplex instruction as a processing element instruction;
(b) examining the mode of operation bit for each simplex instruction by the merged processor to determine if each simplex instruction is a control processor instruction or a processing element instruction;
(c) executing the first simplex instruction by the control processor;
and
(d) executing the second simplex instruction by the processing element;
wherein step (c) and step (d) are performed in parallel.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/783,156Filed 14 Feb 2001 · continuation
Priority: 10 Mar 1998
Published: US 2001/0032303 A118 Oct 2001
Granted: 12 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3885
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units
G06F 9/3012
Register arrangements: organisation of register space, e.g. banked or distributed register file
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30189
Instruction operation extension or modification: according to execution mode, e.g. mode flag

Family

Application60/077,457Us provisional application · filed 10 Mar 1998
Application09/169,072Parent of this continuation · filed 9 Oct 1998
US 2001/0032303 A1Pre-grant publication · published 18 Oct 2001
US 6,219,776 B1Parent of this continuation
US 6,606,699 B2This patent

From the US filing history. Foreign family members aren’t listed.