Information processing apparatus and memory control method
AssigneeHitachi, Ltd.
InventorsKuniaki Kawahara, Yukihiro Seki, Takashi Shimojo
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Abstract
A page table on a main storage contains a correspondence between guest virtual address and a host real address, and a TLB in a processor holds said correspondence calculated by a previous address translation. A PTBR holds a real address of a page table. When a processor detects a TLB purge, the processor starts a host when detecting a TLB purge. The host examines a virtual space change processing executed by the guest, and stores a correspondence between a new guest virtual address and a new host real address in the page table.
Claims8
An information processing apparatus comprising a host program for logically dividing a real memory and allocating divided memory areas to one or a plurality of virtual computers, said apparatus operating an independent guest OS running on the virtual computers, and using a translation table indicating a correspondence between a guest virtual address and a host real address for address translation, comprising:
- an address translation buffer memory (TLB) for holding a pair of a guest virtual address and a host real address which have referred to said translation table;
- means for detecting a purge of said TLB;
- means for generating an exception interrupt when said TLB purge is detected;
- a translation table base register (PTBR) for holding a real memory address in said translation table;
- means for detecting a reading operation of said PTBR;
- means for generating an exception interrupt when the reading operation of said PTBR is detected;
- and
- means for rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt.
A memory control method for constructing a virtual computer by using a translation table indicating a correspondence between a guest virtual address and a host real address for address translation, comprising the steps of:
- holding a pair of guest virtual address and a host real address that have referred to said translation table, in an address translation buffer memory (TLB);
- purging the content of said TLB when said translation table is referred to;
- generating an exception interrupt when said TLB purge is detected;
- rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt;
- calculating the address of the instruction that caused an exception to specify a processing executed;
- and
- rewriting an entry in said translation table when said specified processing is an entry purge.
A memory control method for constructing a virtual computer by using a translation table indicating a correspondence between a guest virtual address and a host real address for address translation, comprising the steps of:
- holding a pair of a guest virtual address and a host real address that have referred to said translation table, in an address translation buffer memory (TLB);
- purging the content of said TLB when said translation table is referred to;
- generating an exception interrupt when said TLB purge is detected;
- rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt;
- reading a translation table base register (PTBR) for holding a real memory address in said translation table;
- generating an exception interrupt, when a reading operation of said PTBR is detected;
- and
- rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt.
A memory control method for constructing a virtual computer by using a translation table indicating a correspondence between a guest virtual address and a host real address for address translation, comprising the steps of:
- holding a pair of a guest virtual address and a host real address that have referred to said translation table, in an address translation buffer memory (TLB);
- purging the content of said TLB when said translation table is referred to;
- generating an exception interrupt when said TLB purge is detected;
- rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt;
- reading a translation table base register (PTBR) for holding a real memory address in said translation table;
- generating an exception interrupt, when a reading operation of said PTBR is detected;
- and
- rewriting the correspondence between the guest virtual address and the host real address in said translation table in response to said generated exception interrupt;
- calculating a guest real address in a guest page table of a guest that has read said PTBR;
- specifying a destination to which a value of said read PTBR is written;
- and
- writing said guest real address to said destination.
A processor performing address translation by referring to a translation table indicating a correspondence between a guest virtual address and a host real address, comprising:
- an address translation buffer memory (TLB) for holding a pair of a guest virtual address and a host real address which have been calculated by said address translation;
- means for detecting a purge of said TLB;
- means for generating an exception interrupt when said TLB purge is detected;
- a translation table base register (PTBR) for holding a real address of said translation table;
- means for detecting a reading operation of said PTBR;
- and
- means for generating an exception interrupt when the reading operation of said PTBR is detected.
Dependencies are inferred from the claim text.