Cache control method and cache controller
AssigneeHitachi, Ltd.
InventorsMasaru Koyanagi, Disuke Yamane, Hideya Akashi, Yuji Tsushima, Tadayuki Sakakibara
Life of this patent
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Abstract
A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.
Claims17
In a computer system equipped with a cache memory between a processor and a main memory, a cache control method comprising the steps of:
- generating a pre-fetch request for said main memory based on a data read request address when a data read request for main memory is issued;
- and
- outputting said data read request and said pre-fetch request, wherein
- said pre-fetch request address is generated using a predetermined block size and stride size,
- calculating an offset address using said data read request address,
- calculating a pre-fetch request count using said block size, and
- calculating a stride width from said offset address using said stride.
In a computer system equipped with a cache memory between a processor and a main memory, a cache controller comprising:
- storing means for storing variables including a pre-fetch block size and stride value;
- generating means for generating access requests for said main memory and at least one pre-fetch request by calculating an offset address using a request from the processor, a pre-fetch request count using said block size, and a stride width from said offset address using said stride;
- and
- means for reading data from said main memory in response to said generated pre-fetch requests and writing said data to said cache memory.
In a computer system equipped with a cache memory between a processor and a main memory, a cache controller comprising:
- registers storing variables, including a pre-fetch block size and stride value;
- a pre-fetch generator generating an access request for said main memory and a pre-fetch request by calculating an offset address with a request from the processor, a pre-fetch request count with said block size, and a stride width from said offset address with said stride value;
- and
- a cache controller reading data from said main memory in response to said generated pre-fetch requests and writing said data to said cache memory.
In a computer system equipped with a cache memory between a processor and a main memory, a cache control method comprising the steps of:
- identifying whether a main memory request is a data read request or a data write request;
- generating a pre-fetch request address based on values set up in a block size register and a stride register when said request is a data read request;
- storing said pre-fetch request address and said data read request address;
- outputting said data read request;
- and
- outputting said pre-fetch request, wherein
- said pre-fetch request address is generated using the values set up in said block size register and said stride register,
- calculating an offset address using said data read request address,
- calculating a pre-fetch request count using the value set up in said block size register, and
- calculating a stride width from said offset address using the value set up in said stride size register.
Dependencies are inferred from the claim text.