Optimized hardware cleaning function for VIVT data cache
AssigneeTexas Instruments Incorporated
InventorsGerard Chauvel, Serge Lasserre, Dominique Benoit Jacques D'Inverno
Life of this patent
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Abstract
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function, the MAX counter (82) counts downward while cache entries at the address given by the MAX counter (82) are written to main memory (16) if the entry is marked as dirty. If an interrupt occurs, the MAX counter is disabled until a subsequent clean request is issued after the interrupt is serviced.
Claims4
A digital system comprising a processor coupled to main memory and a cache memory with dirty bits and having control circuitry for performing a hardware clean function, the control circuitry comprising:
- high circuitry for storing a highest address representative of a highest cache location having dirty data, wherein the high circuitry is operable to compare a pending address of each access to the cache that sets a dirty bit and to update the highest address if the pending address is higher than the current highest address;
- low circuitry for storing a lowest address representative of a lowest cache location having dirty data, wherein the low circuitry is operable to compare the pending address of each access to the cache that sets a dirty bit and to update the lowest address if the pending address is lower than the current lowest address;
- control logic circuitry for writing information from the cache to corresponding main memory locations for each dirty cache location in a range between the lowest address and the highest address in response to a clean function command;
- and
- wherein the control logic circuitry is responsive to the detection of an interrupt to halt the clean function, and to then resume the clean function at a later time.
A method for performing a hardware cache clean function in a system with a cache memory and a main memory, comprising the steps of:
- keeping a record of a highest cache location having dirty data and a lowest cache location having dirty data to form a dirty range of cache locations having potentially dirty cache locations;
- updating the record each time an access is made to the cache that creates a dirty location;
- receiving a function command to clean the cache, and then under control of an autonomous hardware controller performing the steps of:
- generating a series of cache addresses in a predetermined order within the dirty range;
- writing information from each cache location in the dirty range to a corresponding main memory location if the information at the cache location is dirty;
- and
- disabling the series of generated cache addresses responsive to an interrupt and retaining a range indication of a remaining dirty range.
Dependencies are inferred from the claim text.