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US 6,606,684 B1Granted
Multi-tiered memory bank having different data buffer sizes with a programmable bank select
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsHebbalalu S. Ramagopal, Michael Allen, Jose Fridman, Marc Hoffman
Life of this patent
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Abstract
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
Claims9
A system comprising:
- a core processor;
- a cache memory coupled to said core processor, said cache memory having a first block and a second block, where said first block and said second block are connected to said core processor in such a way as to allow substantially simultaneous data accesses for said core processor;
- an address map including
- a first region mapped to the first block, and
- a second region mapped to the second block;
- and a selector operative to
- cache data having an address in said first region of the address map in the first block, and
- cache data having an address in said second region of the address map in the second block,
- wherein said first region and said second region are contiguous regions in the address map.
6 more elements
A method comprising:
- selecting a size of regions in an address map;
- dividing the address map into a plurality of regions of said size;
- mapping adjacent regions in the address map to a different one of two banks in a cache memory, said adjacent regions comprising a first region and a second region contiguous with the first region in the address map;
- caching data having an address in said first region of the address map in one of said two banks;
- and
- caching data having an address in said second region of the address map in the other of said two banks.
3 more elements
An article comprising machine-readable medium including machine-executable instructions operative to cause a machine to:
- select a size of regions in an address map;
- divide the address map into a plurality of regions of said size;
- map adjacent regions in the address map to a different one of two banks in a cache memory, said adjacent regions comprising a first region and a second region contiguous with the first region in the address map;
- cache data having an address in said first region of the address map in one of said two banks;
- and
- cache data having an address in said second region of the address map in the other of said two banks.
3 more elements
Dependencies are inferred from the claim text.