Method and apparatus for accessing banked embedded dynamic random access memory devices

A data processing system comprising:

• a processor;
• a banked embedded DRAM device;
• and
• an embedded DRAM controller, coupled said banked embedded DRAM device to said processor, for controlling said banked embedded DRAM device, wherein said embedded DRAM controller further includes:
• a general functional control logic coupled to each bank of said banked embedded DRAM device;
• and
• a bank RAS controller, coupled to said general functional control logic, wherein said bank RAS controller includes a rotating shift register having multiple bits, wherein each bit within said rotating shift register corresponds to each bank of said banked embedded DRAM device, such that a first value within a bit of said rotating shift register allows accesses to an associated bank of said banked embedded DRAM device, and a second value within a bit of said rotating shift register denies accesses to an associated bank of said banked embedded DRAM device.