Computer system
AssigneeKabushiki Kaisha Toshiba
InventorNobutaka Nakamura
Life of this patent
Estimating the term…
Abstract
In this invention, the bus of a computer body is connected to the bus of an expansion unit through a serial interface so as to implement connection wirings in the form of a serial cable. A PCI-PCI bridge for connecting a primary PCI bus to a secondary PCI bus comprises two physically isolated controllers, i.e., a primary PCI serial transfer controller implemented on the PC body side and a secondary PCI serial transfer controller implemented on the docking station side. The two controllers are connected to each other through serial LVDS lines. Transactions are exchanged between the primary PCI bus and the secondary PCI bus by serial transfer between the primary PCI serial transfer controller and the secondary PCI serial transfer controller.
Claims17
A computer system comprising:
- first and second buses respectively constituted by multiple-bit-width parallel transmission paths;
- a first controller connected to said first bus;
- a second controller connected to said second bus;
- and
- a serial transmission path interposed between said first and second controllers,
- wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path, each of said first and second controllers comprising;
- a bus interface means which operates in synchronous with the same first clock signal as that used by a device on a corresponding one of the first and second buses to exchange a transaction with the corresponding bus, and
- serial transfer means that operates in synchronous with a second clock signal asynchronous to the first clock signal so as to execute serial transfer through the serial transmission path.
A computer system comprising:
- first and second buses respectively constituted by multiple-bit-width parallel transmission paths;
- a first controller connected to said first bus;
- a second controller connected to said second bus;
- a serial transmission path interposed between said first and second controllers,
- wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path;
- wherein said first controller comprises first bus interface means for exchanging a transaction with the first bus;
- wherein said second controller comprises second bus interface means for exchanging a transaction with the second bus;
- and
- wherein said first and second bus interface means operate in synchronous with the first and second clock signals respectively which are asynchronous to each other.
A computer system comprising:
- first and second buses respectively constitute by multiple-bit-width parallel transmission paths;
- a first controller connected to said first bus;
- a second controller connected to said second bus;
- a serial transmission path interposed between said first and second controllers,
- wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path;
- wherein the serial transmission path comprises a full duplex channel including at least one pair of unidirectional serial transmission paths whose signal transmission directions are opposite to each other;
- and
- wherein each of the unidirectional serial transmission paths includes a serial data line for serially transferring the command, address, and data, and a clock signal line for transferring corresponding clock signals.
Dependencies are inferred from the claim text.