US 6,606,677 B1 · High speed interrupt controller

Abstract

A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.

Claims30

Dependent claims

An interrupt recognition method for quick and effective discrimination and management of interrupts and alerts from multiple interrupting sources, used for assisting a processor with limited number of processor interrupt input lines, comprising:

providing an interrupt controller with a plurality of controller interrupt input lines for receiving interrupts and alerts from the interrupting sources, said interrupt controller connected to the processor and having an interrupt status register and an interrupt masking register;
connecting the interrupt status register bits to the corresponding controller interrupt input lines for recognizing individual interrupts according to the interrupt status register bits;
masking the controller interrupt input lines individually by programmably setting and resetting interrupt masking register bits;
and
whereupon an interrupt received on an unmasked controller interrupt input line:
asserting an interrupt signal on a processor interrupt input line,
reading the interrupt status register and the interrupt masking register by the processor, and
servicing the interrupt.

5 more elements

An interrupt controller system for extending capabilities of a processor with limited number of interrupt input lines to accommodate and discriminate interrupts and alerts from a plurality of interrupting sources, comprising:

an interrupt controller connected to the processor via a processor bus and configured to receive a plurality of interrupts and alerts from the plurality of interrupting sources, and to assert an interrupt signal to the processor upon receipt of the interrupt from any of the plurality of interrupting sources;
the interrupt controller having a masking device for enabling and disabling the interrupts from the plurality of interrupting sources individually;
and
a device interrupt handler having program instructions for reading an interrupt status register and the masking device of the interrupt controller, and for recognizing and servicing individual unmasked interrupts according to the interrupting source, upon receipt of the asserted interrupt signal by the processor.

1 more element

A shared bus multi-master data communication system with capabilities of discriminating interrupts and alerts from a plurality of interrupting sources by a processor with limited number of interrupt input lines, comprising:

a shared bus located between an external bus connected to a system processor, and an internal bus connected to an internal processor, said internal processor having a limited number of interrupt input lines;
a plurality of bus masters and corresponding slaves connected to the shared bus, some of said masters associated with the external bus and other said masters associated with the internal bus;
an interrupt controller connected to the internal processor via a processor bus and configured to receive a plurality of interrupts and alerts from the plurality of interrupting sources, and to assert an interrupt signal to the internal processor upon receipt of the interrupt from any of the plurality of interrupting sources;
the interrupt controller having a masking device for enabling and disabling the interrupts from the plurality of interrupting sources individually;
and
a device interrupt handler having program instructions for reading an interrupt status register and the masking device of the interrupt controller, and for recognizing and servicing individual unmasked interrupts according to the interrupting source, upon receipt of the asserted interrupt signal by the internal processor.

3 more elements

Dependencies are inferred from the claim text.

High speed interrupt controller

Life of this patent

High speed interrupt controller

Life of this patent

Abstract

Claims30