Clock synchronization in systems with multi-channel high-speed bus subsystems

An interface circuit that transfers data between a high-speed bus subsystem and other system components, the interface circuit comprising:

• a plurality of bus access circuits configured to transfer data via corresponding channels of the high-speed bus subsystem, each such channel having a channel clock signal, each bus access circuit having a channel clock input configured to receive the channel clock signal of the channel corresponding to the bus access circuit;
• a system clock input configured to receive a system clock signal that indicates a clock phase used by the one or more of the other system components;
• a plurality of clock generators that generate the channel clock signals of the bus channels, each clock generator being associated with one of the bus access circuits and receiving:
• a reference clock signal that has a fixed and known frequency relationship to the system clock signal;
• a local system clock signal that is derived from the system clock signal in the bus access circuit associated with the clock generator, the local system clock signal having a known and fixed frequency relationship with the system clock signal;
• a local channel clock signal that is derived from the channel clock signal received by the bus access circuit, the local channel clock signal having a known and fixed frequency relationship with said channel clock signal;
• each clock generator being configured to adjust the phase of its channel clock signal to align the phases of the local system clock signal and the local channel clock signal received by the clock generator.

A method of synchronizing bus channel clock signals in a high-speed bus subsystem having a plurality of high-speed data communications channels, each high-speed data communications channel having a channel clock signal whose phase varies along the length of the channel because of propagation delays, the high-speed bus subsystem having a plurality of bus access circuits in an integrated circuit that transfers data via corresponding channels of the high-speed bus subsystem;

• the method comprising:
• receiving the channel clock signal of the channel corresponding to the bus access circuit;
• receiving a system clock signal that indicates a clock phase used by components outside of the high-speed bus subsystem;
• generating a local channel clock signal within each bus access circuit, the local channel clock signal having a known and fixed frequency relationship with the channel clock signal received by the bus access circuit;
• generating a local system clock signal within the integrated circuit, the local system clock signal having a known and fixed frequency relationship with the system clock signal;
• generating a reference clock signal that has a fixed and known frequency relationship to the system clock signal;
• receiving the following signals at each of a plurality of clock generators that are associated with the respective bus access circuits to generate the channel clock signals:
• the reference clock signal;
• the local system clock signal of the bus access circuit associated with the clock generator;
• the local channel clock signal of the bus access circuit associated with the clock generator;
• within each clock generator, adjusting the phase of the channel clock signal to align the phases of the local system clock signal and the local channel clock signal received by the clock generator.