Method and apparatus for estimating elmore delays within circuit designs
AssigneeHewlett-Packard Development Company, L.P.
InventorsNevine Nassif, Madhav Desai, Dale Hayward Hall
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Abstract
A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.
Claims16
A timing verification system including representation of a circuit comprising:
- path means for determining a discharge path through the circuit, wherein the discharge path includes at least one device;
- model selection means for selecting an Elmore delay model, from a plurality of Elmore delay models, for each of the at least one device;
- delay determining means for determining a path Elmore delay based upon the Elmore delay models selected for the at least one device.
A method of timing verification comprising the steps of:
- determining a discharge path through a circuit, wherein the discharge path includes at least one device;
- selecting an Elmore-delay model from a plurality of Elmore delay models, for each device in a discharge path;
- and
- determining a path Elmore delay based upon the Elmore-delay models selected for each device;
- wherein said Elmore-delay model is defined as τmVDD=k2Q/W+k1L/W+k0, τm is an Elmore delay, VDD is the circuit's high voltage value, Q is a charge across the device, W is the device's width, L is the device's length, and k0, k1, and k2 are coefficents that vary with circuit conditions.
A system for creating Elmore delay models for devices within a circuit design comprising:
- means for representing a plurality of devices within a set of circuit structures;
- means for simulating operation of the set of circuit structures and determining an Elmore delay value for each of the plurality of devices based upon a set of device parameters;
- and
- means for applying curve fitting to the Elmore delay values to create an Elmore delay model for each of the plurality of devices based upon the set of device parameters.
Dependencies are inferred from the claim text.