Modified first-order digital PLL with frequency locking capability

A first-order digital phase-locked loop configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by the phase locked loop and a local reference clock signal received by the phase-locked loop circuit, said phase-locked loop comprising:

• a data sampler which receives the incoming data steam;
• a frequency-locked loop which receives the incoming data stream and is connected to said data sampler;
• and a frequency synthesizer which receives the local reference clock signal and is connected to said frequency-locked loop, wherein said frequency-locked loop is configured to provide a first signal to said data sampler when no incoming data stream is received by said frequency-locked loop circuit, wherein the first signal has a frequency which is substantially equal to a frequency of the local reference clock signal, and wherein said frequency-locked loop is configured to provide a second signal to said data sampler when said frequency-locked loop receives the incoming data stream, wherein the second signal has a frequency which is substantially equal to a frequency of the incoming data stream, wherein both said frequency-locked loop and said frequency synthesizer include a phase/frequency detector, a charge pump coupled to said phase/frequency detector, a loop filter connected to said charge pump, a voltage-to-current converter coupled to said loop filter, and a current-controlled oscillator connected to said voltage-to-current converter, wherein said frequency-locked loop is configured to disconnect said loop filter of said frequency-locked loop from said charge pump of said frequency-locked loop when no incoming data stream is received by said frequency-locked loop circuit, and wherein said frequency-locked loop is configured to connect said loop filter of said frequency-locked loop to said charge pump of said frequency-locked loop when said frequency-locked loop receives the incoming data stream.

A first-order digital phase-locked loop configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by the phase-locked loop and a local reference clock signal received by the phase-locked loop circuit, said phase-locked loop comprising:

• a data sampler which receives the incoming data stream a frequency-locked loop which receives the incoming data stream and is connected to said data sampler;
• and a frequency synthesizer which receives the local reference clock signal and is connected to said frequency-locked loop, wherein said frequency-locked loop is configured to provide a first signal to said data sampler when no incoming data stream is received by said frequency-locked loop circuit, wherein the first signal has a frequency which is substantially equal to a frequency of the local reference clock signal, and wherein said frequency-locked loop is configured to provide a second signal to said data sampler when said frequency-locked loop receives the incoming data stream, wherein the second signal has a frequency which is substantially equal to a frequency of the incoming data stream, wherein the incoming data stream includes a synchronization field and a data field, wherein the synchronization field precedes the data field, wherein said frequency-locked loop is configured to provide the second signal to said data sampler while said synchronization field is being received by the phase-locked loop circuit.

A first-order digital phase-locked loop configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by the phase-locked loop and a local reference clock signal received by the phase-locked loop circuit, said phase-locked loop comprising:

• a data sampler which receives the incoming data stream;
• a frequency-locked loop which receives the incoming data stream and is connected to said data sampler;
• and a frequency synthesizer which receives the local reference clock signal and is connected to said frequency-locked loop, wherein said frequency-locked loop is configured to provide a first signal to said data sampler when no incoming data stream is received by said frequency-locked loop circuit, wherein the first signal has a frequency which is substantially equal to a frequency of the local reference clock signal, wherein said frequency-locked loop is configured to provide a second signal to said data sampler when said frequency-locked loop receives the incoming data stream, wherein the second signal has a frequency which is substantially equal to a frequency of the incoming data stream, wherein each of said frequency-locked loop and said frequency synthesizer includes a phase/frequency detector, a charge pump connected to said phase/frequency detector, a loop filter coupled to said charge pump, a voltage-to-current converter connected to said loop filter, and a current-controlled oscillator coupled to said voltage-to-current converter, wherein said frequency-locked loop is configured to connect said loop filter of said frequency-locked loop to said charge pump of said frequency-locked loop when said frequency-locked loop receives the incoming data stream, wherein said current-controlled oscillator of said frequency-locked loop is configured to selectively operate at the frequencies of the local reference clock signal and the incoming data stream and is configured to provide the first and second signals to said data sampler, wherein said frequency-locked loop further includes a switch between said charge pump and said loop filter, and wherein said frequency-locked loop further includes a counter which receives the incoming data stream and is configured to control said switch, wherein the incoming data stream includes a synchronization field and a data field, wherein the synchronization field precedes the data field, wherein said frequency-locked loop is configured to provide the second signal to said data sampler while said synchronization field is being received by the phase-locked loop circuit.

A first-order digital phase-locked loop configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by the phase-locked loop and a local reference clock signal received by the phase-locked loop circuit said phase-locked loop comprising:

• a data sampler which receives the incoming data stream, a frequency-locked loop which receives the incoming data stream and is connected to said data sampler;
• and a frequency synthesizer which receives the local reference clock signal and is connected to said frequency-locked loop, wherein said frequency-locked loop includes a current-controlled oscillator which is configured to selectly operate at a frequency of the local reference clock signal or a frequency of the incoming data stream and is configured to provide a signal to said data sampler, wherein said current-controlled oscillator of said frequency-locked loop is configured to provide a first signal to said data sampler when no incoming data stream is received by said frequency-locked loop, wherein the first signal has a frequency which is substantially equal to the frequency of the local reference clock signal, and wherein said frequency-locked loop is configured to provide a second signal to said data sampler when said frequency-locked loop receives the incoming data stream, wherein the second signal has a frequency which is substantially equal to the frequency of the incoming data streams, wherein said frequency-locked loop includes a charge pump and a loop filter, and said frequency-locked loop is configured to disconnect said loop filter from said charge pump when no incoming data stream is received by said frequency-locked loop circuit, and wherein said frequency-locked loop is configured to connect said loop filter to said charge pump when said frequency-locked loop receives the incoming data stream.