Multiple data rate bit synchronizer having phase/frequency detector gain constant proportional to PLL clock divider ratio

A method of generating an output frequency signal that is synchronized with the clock rate of an input data signal having a baud rate which may vary over a prescribed range, comprising the steps of:

• (a) providing a phase locked loop PLL that includes
• a clock frequency generator,
• a variable divider, from which the output frequency signal is derived and being operative to divide an output frequency signal generated by said clock frequency generator by a variable divisor and producing therefrom a divided clock signal having a frequency corresponding to said data rate and which may fall anywhere within said prescribed range,
• a phase/frequency detector coupled to receive said input data signal and said divided clock signal produced by said variable divider, and being operative to generate an output representative of the phase/frequency difference between said input data signal and said divided clock signal, and
• a loop filter coupled in circuit with said phase/frequency detector and said clock frequency generator;
• and
• (b) maintaining the bandwidth of said PLL constant over said prescribed range by configuring said phase/frequency detector to have a gain constant that is proportional to said variable divider, and comprising configuring said phase/frequency detector as a phase/frequency detector circuit that is operative to produce an output current in accordance with the phase/frequency difference between said input data signal and said divided clock signal, and an integrator that is operative to generate an output voltage representative of the integral of said output current.

An apparatus for generating an output frequency signal that is synchronized with the clock rate of an input data signal that has a baud rate that varies over a prescribed range, the apparatus comprising:

• a clock frequency generator;
• a variable divider to divide an output frequency signal generated by said clock frequency generator by a variable divisor and produce therefrom a divided clock signal having a frequency corresponding to said clock rate and which is within said prescribed range;
• a phase/frequency detector having a gain constant that is proportional to said variable divisor, an output representative of a phase/frequency difference between the input data signal and said divided clock signal, and comprising
• a first input to receive said input data signal,
• a second input to receive said divided clock signal produced by said variable divider,
• a phase/frequency detector circuit coupled to said first and second inputs, said phase/frequency detector circuit to produce an output current in accordance with a phase/frequency difference between said input data signal and said divided clock signal, and
• an integrator to generate an output voltage based on an integral of said output current;
• and
• a loop filter coupled in circuit with said phase/frequency detector and said clock frequency generator.

An apparatus for generating an output frequency signal that is synchronized with the clock rate of an input data signal that has a baud rate which varies over a prescribed range, the apparatus comprising:

• a clock frequency generator;
• a variable divider to divide an output frequency signal generated by said clock frequency generator by a variable divisor and producing therefrom a divided clock signal having a frequency corresponding to said clock rate and which falls within said prescribed range;
• a phase/frequency detector having a gain constant that is proportional to said variable divisor, an output current representative of a phase/frequency difference between the input data signal and said divided clock signal, and comprising
• a first input to receive said input data signal,
• a second input to receive said divided clock signal produced by said variable divider, a capacitor,
• a charge pump to charge said capacitor with said output current, and
• a resistor coupled to said capacitor and said charge pump to generate an output voltage representative of the integral of said output current;
• and
• a loop filter coupled between said integrating resistor and said clock frequency generator.

A method of generating an output frequency signal that is synchronized with the clock rate of an input data signal having a baud rate which may vary over a prescribed range, comprising the steps of:

• (a) providing a phase locked loop PLL that includes
• a clock frequency generator, said clock frequency generator generating a fixed output frequency signal that is at least an order of magnitude higher than the highest baud rate of said prescribed range, and said prescribed range covering plural orders of magnitude of baud rate variation,
• a variable divider, from which the output frequency signal is derived and being operative to divide an output frequency signal generated by said clock frequency generator by a variable divisor and producing therefrom a divided clock signal having a frequency corresponding to said data rate and which may fall anywhere within said prescribed range,
• a phase/frequency detector coupled to receive said input data signal and said divided clock signal produced by said variable divider, and being operative to generate an output representative of the phase/frequency difference between said input data signal and said divided clock signal, and
• a loop filter coupled in circuit with said phase/frequency detector and said clock frequency generator;
• and
• (b) maintaining the bandwidth of said PLL constant over said prescribed range by configuring said phase/frequency detector to have a gain constant that is proportional to said variable divider.