Circuits, systems, and methods for providing a single output clock and output data stream from an interface having multiple clocks and an input data stream

A circuit for producing a single output data stream and a corresponding single clock signal comprising:

• an input for receiving a single input data stream, the input data stream having data words at a first frequency;
• a plurality of clock inputs for receiving a plurality of corresponding clock signals, wherein each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of data words;
• an input for receiving a fast clock signal, the fast clock signal having a fast frequency greater than the first frequency;
• circuitry for sampling the input data stream at the fast frequency;
• circuitry for outputting the sampled data as the single output data stream;
• circuitry for outputting the single clock signal in response to the fast clock signal;
• wherein the plurality of clock inputs consists of two clock inputs;
• and
• wherein the plurality of corresponding clock signals consists of a first clock signal and a second clock signal;
• wherein the circuitry for sampling the input data stream comprises:
• a first latch having a data input coupled to the input for receiving the single input data stream, the first latch coupled to be clocked by the first clock signal;
• a second latch having a data input coupled to the input for receiving the single input data stream, the second latch coupled to be clocked by the second clock signal;
• a third latch having a data input coupled to an output of the first latch, the third latch coupled to be clocked by the fast clock signal;
• and
• a fourth latch having a data input coupled to the output of the second latch, the fourth latch coupled to be clocked by the fast clock signal.

A method for producing a single output data stream and a corresponding single clock signal, comprising:

• receiving a single input data stream, the input data stream having data words at a first frequency;
• receiving a plurality of corresponding clock signals, wherein each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words;
• receiving a fast clock signal, the fast clock signal having a fast frequency greater than the first frequency;
• sampling the input data stream at the fast frequency;
• outputting the sampled data as the single output data stream;
• outputting the single clock signal in response to the fast clock signal;
• wherein the fast clock signal consists of successive periods, wherein each of the successive periods consists of a high state and a low state;
• and
• wherein the step of outputting the single clock signal comprises outputting a modified clock signal representing selected ones of the successive periods of the fast clock signal such that the modified clock signal transitions only once for each data word in the single output data stream.