Area-optimum rapid acquisition cellular multi-protocol digital DC offset correction scheme
AssigneeMotorola, Inc.
InventorsManbir Nag, James Mittel
Life of this patent
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Abstract
A digital DC offset correction circuit (68) provides DC offset correction within a receiver (50) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit (68) includes an integrator (90), a low pass filter (92), a decimator (94), a digital to analog converter codeword clamp (96), and a digital to analog converter (98).
Claims9
A receiver for receiving and processing a radio frequency signal using an area-optimum rapid acquisition cellular multi-protocol digital dc offset correction scheme within a radio communication system, the receiver comprising:
- a receiver antenna for receiving the radio frequency signal;
- a radio frequency frontend coupled to the receiver antenna for receiving the radio frequency signal and for generating a desired signal;
- a post mixer amplifier coupled to the radio frequency frontend receiving the desired signal and for generating a post mixer amplifier output;
- a first anti-alias filter coupled to the post mixer amplifier for generating a first anti-alias filter output;
- a summing junction coupled to the first anti-alias filter for receiving the first anti-alias filter output and an offset correction signal and for generating a combined intermediate frequency signal;
- an intermediate frequency amplifier circuit coupled to the summing junction for receiving the combined intermediate frequency signal and for generating an intermediate frequency amplifier output;
- a second anti-alias filter coupled to the intermediate frequency amplifier circuit receiving the intermediate frequency amplifier output and for generating a second anti-alias filter output;
- an analog to digital converter coupled to the second anti-alias filter for receiving the second anti-alias filter output and for generating a most significant bit and a least significant bit;
- and
- a digital DC offset correction circuit coupled between the analog to digital converter and the summing junction, for receiving the least significant bit and for generating the offset correction signal.
A digital DC offset correction circuit for providing DC offset correction within a receiver for receiving and processing a radio frequency signal using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme within a radio communication system, the receiver including an analog to digital converter and a clock, the digital DC offset correction circuit comprising:
- an integrator, for receiving a least significant bit from the analog to digital converter and for generating an integrator output;
- a low pass filter coupled to the integrator for receiving the integrator output and for generating a low pass filter output;
- a decimator coupled to the low pass filter for receiving the low pass filter output and for generating a decimator output;
- a digital to analog converter codeword clamp coupled to the decimator for receiving the decimator output and for generating a clamped signal;
- and
- a digital to analog converter coupled to the digital to analog converter codeword clamp for receiving the clamped signal and for generating an offset correction signal.
Dependencies are inferred from the claim text.