Asynchronous digital system, asynchronous data path circuit, asynchronous digital signal processing circuit and asynchronous digital signal processing method

An asynchronous digital signal processing circuit for processing input data d1 to generate new data d2,

• wherein said circuit includes a completion signal generation circuit for generating a completion signal indicating that said new data d2 has become valid,
• said completion signal generation circuit comprises circuit components having an assumed delay in which k·Td<Ts is established wherein Td is the time since said input data d1 becomes valid until said new data d2 becomes valid, Ts is the time since said input data d1 becomes valid until said completion signal is generated, and (k) is a constant which is a real number larger than 1.

A digital system comprising one or more first digital signal processing system(s) and one or more second digital signal processing system(s),

• wherein said first digital signal processing system controls processing timing of digital signals using clock signals, and
• wherein said second digital signal processing system includes circuit components having an assumed delay in which if the implementation of a function requires that a first signal transition (a) occurs to cause a second signal transition (b) and a third signal transition (c) and that said second signal transition (b) precedes said third signal transition (c), k·Tab<Tac is established wherein Tab is the time from the occurrence of said first signal transition (a) until the occurrence of said second signal transition (b), Tac is the time from the occurrence of said first signal transition (a) until the occurrence of said third signal transition (c), and (k) is a constant which is a real number larger than 1.

A semiconductor chip on which one or more first digital signal processing system(s) and one or more second digital signal processing system(s) are provided,

• wherein said first digital signal processing system controls processing timing of digital signals using clock signals, and
• wherein said second digital signal processing system includes circuit components having an assumed delay in which if the implementation of a function requires that a first signal transition (a) occurs to cause a second signal transition (b) and a third signal transition (c) and that said second signal transition (b) precedes said third signal transition (c), k·Tab<Tac is established wherein Tab is the time from the occurrence of said first signal transition (a) until the occurrence of said second signal transition (b), Tac is the time from the occurrence of said first signal transition (a) until the occurrence of said third signal transition (c), and (k) is a constant which is a real number larger than 1.

A digital system comprising one or more synchronous digital signal processing circuit(s) and one or more asynchronous digital signal processing circuit(s),

• wherein said asynchronous digital signal processing circuit processes input data d1 to generate new data d2, and
• includes a completion signal generation circuit for generating a completion signal indicating that said new data d2 has become valid,
• said completion signal generation circuit comprises circuit components having an assumed delay in which k·Td<Ts is established wherein Td is the time since said input data d1 becomes valid until said new data d2 becomes valid, Ts is the time since said input data d1 becomes valid until said completion signal is generated, and (k) is a constant which is a real number larger than 1.