Dual key controlled content addressable memory for accessing packet switch data buffer for multicasting data packets
AssigneeHarris Corporation
InventorsEdward R. Beadle, John F. Dishman
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AssigneeHarris Corporation
InventorsEdward R. Beadle, John F. Dishman
Estimating the term…
An output port centric digital data management architecture for a high speed packet switch employs a dual key-based content addressable memory (CAM)-based buffer access control mechanism for efficient storage and read out of relatively long data packets to one or more output ports of the switch. The CAM stores respectively different address pointer words, each containing a respectively different key field to identify a data packet to be delivered to a switch output port, and an address field that identifies the address of one of the storage locations of the packet buffer in which the data packet is stored. During a first portion of a dual key CAM search, a packet request key is coupled to the key fields of all address pointer words stored in the CAM. The location of the matching key is used to access the key field's companion address field in its address pointer word during a second portion of the dual search of the CAM. During this second search, the accessed address field is read out so as to access a data packet stored in the packet buffer, and is also simultaneously coupled to address fields of all the address pointer words stored in the CAM. In response to this second search, the CAM outputs a signal representative of whether the accessed address field is contained in the address field of another address pointer word stored in the CAM, thereby indicating whether or not the buffer address from which the packet has been accessed is free to store new data.
For use with a communication system in which a data packet is to be multicast to a plurality of recipients, a method of buffering and controllably supplying said data packet for delivery to multiple ones of a plurality of output ports associated with said recipients comprising the steps of:
A content-addressable memory having a plurality of storage regions that store respectively different address pointer words, a respective storage region containing:
For use with a communication system in which packetized data is to be controllably multicast to a plurality of recipients in accordance with multicast criteria, an output port data distribution architecture for buffering and controllably supplying packetized data for delivery to multiple ones of a plurality of output ports associated with said recipients comprising:
For use with a communication system in which a data packet is to be multicast to a plurality of recipients, a method of buffering and controllably supplying said data packet for delivery to multiple ones of a plurality of output ports associated with said recipients comprising the steps of:
An output port centric digital data management architecture for a high speed packet switch comprising a content addressable memory which stores address information for controlling multiple accesses to the same data packet stored in a single memory address of a data packet output buffer, to selectively read out therefrom said same data packet to a plurality of ports of the switch, said content addressable memory being configured to store respectively different buffer address pointer words that identify said same data packet to be delivered to selected ones of said plurality of switch output ports, and point to the address of said single storage location of said packet buffer.
A content-addressable memory comprising an array of storage regions that store multibit words, each storage region being formed of a first plurality of content addressable memory cells, the contents of which are associated with a first field of a respective multibit word, and a second plurality of content addressable memory cells, the contents of which are associated with a second field of said respective multibit word, and wherein respectively different words stored in multiple ones of said plurality of storage regions of said content addressable memory contain respectively different first fields, and a common second field.
Dependencies are inferred from the claim text.