Semiconductor memory device
AssigneeHitachi, Ltd.
InventorYasuhiko Takahashi
Life of this patent
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Abstract
To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.
Claims20
A semiconductor memory device which outputs read data to a data terminal in a data read operation in synchronism with a synchronization signal and inputs write data in a data write operation via said data terminal in synchronism with a synchronization signal, wherein:
- in a first time period when the output of read data to the data terminal should be performed, the input/output operation which permits input of write data via the data terminal is permitted;
- and
- a second time period after a write operation until the input of a write data is started, and a third time period when the input of write data is performed are provided, and output of said read data to the data terminal is permitted within the second time period.
A semiconductor memory comprising a synchronized bi-directional interface which performs data transmission in a read operation and a write operation in synchronism with a clock signal, and having a function wherein:
- registration of a write operation is enabled within a clock signal time period when read data should be output via the interface in said read operation;
- and
- when a write operation is specified within the clock signal time period when read data should be output, the output of data is temporarily suspended before starting the input of write data, write data is input, and the suspended output of read data is resumed after completing input of the write data.
A semiconductor memory device, comprising
- a plurality of memory banks, and a synchronized bi-directional interface common to the plurality of memory banks which outputs read data and inputs write data in synchronism with a clock signal, which permits read and write operation specifications according to a memory bank specification, and wherein,
- when one read operation is specified, read data is output from a timing at which the operation was specified, from a memory bank specified after a first period which is an integral multiple of a unit period set by the clock signal via the synchronized bi-directional interface has elapsed, and
- when one write operation is specified, data written to a specified memory bank is acquired from a timing at which the operation was specified via the synchronized bi-directional interface after a second period which is an integral multiple of a unit period set by the clock signal has elapsed,
- wherein said device can respond to a plurality of sequential read operation specifications or a plurality of sequential write operation specifications at each unit period set by the clock signal regardless of the first or second period corresponding to the preceding operation specifications, and
- when a write operation is specified before the termination of the read operation, output of read data via the synchronized bi-directional interface is permitted until a second period corresponding to this write operation specification, and write data is then acquired via the synchronized bi-directional interface after the second period has elapsed.
Dependencies are inferred from the claim text.