SRAM device using MIS transistors
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsHiroyuki Yamauchi, Kazuo Itoh
Life of this patent
Estimating the term…
Abstract
An SRAM device according to the present invention comprises a memory cell including a first pair of bit lines connected to a first port, a second pair of bit lines connected to a second port, a first inverter, and a second inverter having an input terminal connected to the output terminal of the first inverter and an output terminal connected to the input terminal of the first inverter. The memory cell has a first region in which an impurity of a first conductivity type is diffused and second and third regions each of a second conductivity type which are adjacent to the first region and opposed to each other with the first region interposed therebetween. The first pair of bit lines are disposed on the second region and the second pair of bit lines are disposed on the third region.
Claims12
An SRAM device comprising a memory cell, the memory cell including:
- a first pair of bit lines connected to a first port;
- a second pair of bit lines connected to a second port:
- a first inverter;
- and
- a second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the first inverter,
- the memory cell having a first region in which an impurity of a first conductivity type is diffused and second and third regions each of a second conductivity type, the second and third regions being adjacent to the first region and opposed to each other with the first region interposed therebetween,
- the first pair of bit lines being disposed on the second region and the second pair of bit lines being disposed on the third region.
Dependencies are inferred from the claim text.