Methods and systems for flash memory tunnel oxide reliability testing
AssigneeAdvanced Micro Devices, Inc.
InventorsXin Guo, Nian Yang, Zhigang Wang
Life of this patent
Estimating the term…
Abstract
Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise measuring an initial threshold voltage of a test cell having the same tunnel oxide as other flash cells on the wafer, applying an erase stress to the test cell for a first time period and a program stress to the test cell for a second time period, and measuring the final threshold voltage of the test cell. The difference between the initial and final threshold voltages is then used to determine or estimate the tunnel oxide reliability of the flash memory cells on the wafer.
Claims21
A method for testing tunnel oxide reliability of flash memory devices in a semiconductor wafer, comprising:
- measuring an initial threshold voltage associated with a flash memory cell in the semiconductor wafer;
- applying a first stress to a tunnel oxide of the flash memory cell for a first time period, application of the first stress for the first time period being equivalent to N erase operations, N being an integer greater than 1;
- applying a second stress to the tunnel oxide of the flash memory cell for a second time period, application of the second stress for the second time period being equivalent to N program operations;
- measuring a final threshold voltage associated with the flash memory cell following the first and second stresses;
- and
- determining a tunnel oxide reliability for flash memory devices in the semiconductor wafer according to the initial and final threshold voltages.
A method of estimating tunnel oxide reliability of flash memory devices in a wafer, comprising:
- providing a test cell having a source, a drain, and a channel in a substrate of the wafer, a gate, and a tunnel oxide separating the channel from the gate;
- applying an erase stress to a tunnel oxide of the test cell equivalent to N erase operations, N being an integer greater than 1;
- applying a program stress to the tunnel oxide of the test cell equivalent to N program operations;
- measuring a threshold voltage shift associated with application of the erase and program stresses to the test cell;
- and
- estimating a tunnel oxide reliability for flash memory devices in the wafer according to the threshold voltage shift.
A system for testing tunnel oxide reliability of flash memory devices in a wafer, comprising:
- a test circuit operable to apply an erase stress to a tunnel oxide of a test cell equivalent to N erase operations and to apply a program stress to the tunnel oxide of the test cell equivalent to N program operations, N being an integer greater than 1;
- means for measuring a threshold voltage shift associated with the test cell;
- and
- means for selectively accepting or rejecting the flash memory devices in the wafer according to the threshold voltage shift.
Dependencies are inferred from the claim text.