Method and circuit for processing output data in pipelined circuits

A method of operating a pipelined circuit having a maximum latency of N, the method comprising:

• converting data from a serial bit stream to N−1 parallel bits of data;
• steering the N−1 parallel bits of data into N−1 output registers;
• converting the N−1 parallel bits of data into serial data,
• wherein when the circuit operates with a latency of N, the conversion utilizes output enable signals having a first pulse width, and when the circuit operates with a latency of less than N, the conversion utilizes output enable signals having a second pulse width.

A data transmission circuit comprising:

• an output terminal;
• a plurality of data registers each coupled between the output terminal and a data bus, each storing successive data bits received serially from the data bus;
• a plurality of enable signals each coupled to a corresponding data register, wherein when one of the plurality of enable signals is active a data bit in the corresponding data register is coupled to the output terminal and when one of the plurality of enable signals is inactive a data bit in the corresponding data register is not coupled to the output terminal;
• and
• a mode select circuit to program the plurality of enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the enable signals have a first pulse width and in a second mode the enable signals have a second pulse width greater than the first pulse width.

A method of transmitting data to an output terminal of a data transmission circuit comprising:

• programming a latency period;
• programming a plurality output enable signals to operate in one of a plurality of modes corresponding to the latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width;
• sequentially storing output data in a plurality of output registers, wherein each output register is coupled to the output terminal;
• generating the plurality of output enable signals;
• and
• coupling each of the plurality of output enable signals to a corresponding one of the plurality of output registers, wherein each output enable signal selectively couples a data bit in a corresponding output register to the output terminal.