Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing

A wafer comprising:

• at least one memory device including:
• a conductor configured to distribute a boosted voltage within the at least one memory device;
• internal boosting circuitry operably coupled to the conductor and configured to boost a voltage level on the conductor upon sensing that the voltage level has fallen below a minimum level;
• a terminal configured to receive current from a current source external to the at least one memory device;
• and
• a switching circuit operably coupled to the conductor, the internal boosting circuitry, and the terminal, the switching circuit configured to conduct current received through the terminal to the conductor in response to the internal boosting circuitry sensing that the voltage level on the conductor has fallen below the minimum level.

A semiconductor substrate comprising:

• at least one Dynamic Random Access Memory (DRAM) device, said at least one DRAM device comprising:
• a boosted voltage bus;
• a voltage regulator operably coupled to the boosted voltage bus and configured to sense whether a boosted voltage has fallen below a minimum level;
• a ring oscillator operably coupled to the voltage regulator and configured to output a clock signal in response to the voltage regulator sensing that the boosted voltage has fallen below the minimum level;
• a charge pump operably coupled to the ring oscillator and the boosted voltage bus, the charge pump configured to boost the boosted voltage in response to the clock signal;
• a bond pad configured to receive current from a current source external to the at least one DRAM device;
• and
• a switching circuit operably coupled to the boosted voltage bus, the ring oscillator, and the bond pad and configured to conduct current received through the bond pad to the boosted voltage bus in response to the clock signal.

A semiconductor wafer having multiple semiconductor dice interconnected in rows and columns, said wafer comprising:

• at least one semiconductor device including:
• internal boosting circuitry operably coupled to a conductor;
• and
• a terminal operably coupled to a point external to the at least one semiconductor device and configured to conduct current received through the terminal to the conductor in response to the internal boosting circuitry sensing that a voltage on the conductor has fallen below a minimum level.