Nonvolatile semiconductor memory device capable of writing multilevel data at high rate
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakahiro Tsuruda
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Abstract
A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.
Claims8
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix, wherein
- said memory cells include storage elements capable of storing multilevel data in a nonvolatile manner, and
- each of said storage elements has a first node and a second node, and a threshold level of each of said storage elements changed in the nonvolatile manner by applying a voltage at least between said first node and said second node is capable of having one of a plurality of levels corresponding to said multilevel data;
- a plurality of word lines provided to correspond to rows of said memory cell array, and coupled to said first node of each of said storage elements belonging to the corresponding rows, respectively;
- a row select circuit capable of selectively supplying a first pulse potential to each of said plurality of word lines in a write operation;
- a plurality of bit lines provided to correspond to columns of said memory cell array, and coupled to said second node of each of said storage elements belonging to the corresponding columns, respectively;
- a plurality of program data circuits provided to correspond to said plurality of bit lines, and supplying one of a second potential and a write prohibiting potential corresponding to the multilevel data to be written to said storage elements connected to the corresponding bit lines, to said corresponding bit lines in accordance with a write control signal in the write operation, respectively;
- and
- a plurality of program sense circuits provided to correspond to said plurality of bit lines, comparing threshold values of said storage elements sensed through the corresponding bit lines with reference potentials corresponding to said multilevel data to be written in a verification operation, and instructing output of the write prohibiting potential by said write control signal if said threshold values become values corresponding to said multilevel data to be written, respectively.
Dependencies are inferred from the claim text.