Method and apparatus for equalizing the digital performance of multiple ADC's
AssigneeMarvell International Ltd.
InventorSehat Sutardja
Life of this patent
Estimating the term…
Abstract
Method and apparatus for equalizing the digital performance of multiple ADCs includes structure and/or steps for coupling at least one global line between the ADC's resistor ladders to allow current to flow therebetween to balance the reference voltages applied to the comparators of the ADCs. Preferably, the reference voltages are applied equally between the resistor ladders. Even more preferably, the ADC's comparators are located close to each other on a monolithic CMOS circuit.
Claims62
Apparatus for equalizing first and second Analog-to-Digital converters, which have corresponding first and second resistor strings, comprising:
- a positive reference voltage terminal;
- a negative reference voltage terminal;
- a global line coupling together the first resistor string and the second resistor string at a point spaced from both the positive reference voltage terminal and the negative reference voltage terminal;
- a positive reference voltage line coupling together a first portion of the first resistor string and a first portion of the second resistor string, the positive reference voltage terminal being coupled to said positive reference voltage line at substantially a midpoint thereof, and
- a negative reference voltage line coupling together a second portion of the first resistor string and a second portion of the second resistor string, the negative reference voltage terminal being coupled to said negative reference voltage line at substantially a midpoint thereof.
ADC apparatus comprising;
- a first ADC having a first decoder, a first plurality of comparators, a first switching circuit, a first RAM, and a first resistor ladder;
- a second ADC having a second decoder, a second plurality of comparators, a second switching circuit, a second RAM, and a second resistor ladder;
- positive voltage wiring coupled to first ends of said first and second resistor ladders;
- negative voltage wiring coupled to second ends of said first and second resistor ladders;
- a positive reference terminal coupled to a midpoint of said positive voltage wiring;
- a negative voltage terminal coupled to a midpoint of said negative voltage line;
- and
- a global line coupled between said first and second resistor ladders to tend to equalize current flowing in said first and second resistor ladders.
Circuitry for equalizing two time-interleaved ADCs, which have corresponding first and second resistor strings, comprising:
- a reference voltage line coupling together the first and second resistor strings;
- a reference voltage terminal coupled to said reference voltage line at substantially a midpoint thereof;
- and
- a global line coupling together the first and second resistor strings at a location spaced apart from said reference voltage line.
Disk channel read channel apparatus for equalizing first and second Analog-to-Digital converters, which have corresponding first and second resistor strings, comprising;
- positive reference voltage terminal;
- a negative reference voltage terminal;
- a positive reference voltage line coupling together a first portion of the first resistor string and a first portion of the second resistor string, the positive reference voltage terminal being coupled to said positive reference voltage line at substantially a midpoint thereof;
- and
- a negative reference voltage line coupling together a second portion of the first resistor string and a second portion of the second resistor string, the negative reference voltage terminal being coupled to said negative reference voltage line at substantially a midpoint thereof;
- and
- a global line in the read channel and coupling together the first resistor string and the second resistor string at a point spaced from both the positive reference voltage terminal and the negative reference voltage terminal.
Apparatus for equalizing first and second Analog-to-Digital converters, which have corresponding first and second resistor strings, comprising:
- means for providing a positive reference voltage;
- means for providing a negative reference voltage;
- means for coupling together the first resistor string and the second resistor string at a point spaced from both the means for providing the positive reference voltage and the means for providing the negative reference voltage, to cause current to flow between said resistor strings;
- means for coupling together a first portion of the first resistor string and a first portion of the second resistor string, the means for providing the positive reference voltage being coupled said means for coupling together the first portion of the first resistor string and the first portion of the second resistor string at substantially a midpoint thereof;
- and
- means for coupling together a second portion of the first resistor string and a second portion of the second resistor string, the means for providing a negative reference voltage being coupled to said means for coupling together the second portion of the first resistor string and the second portion of the second resistor string at substantially a midpoint thereof.
Apparatus for equalizing two time-interleaved ADCs, which have corresponding first and second resistor strings, comprising:
- means for delivering a reference voltage coupled to the first and second resistor strings;
- means for applying the reference voltage coupled to a point substantially at midpoint of said means for delivering the reference voltage;
- and
- means for coupling together the first and second resistor strings at a location spaced apart from said means for delivering the reference voltage.
A method for equalizing first and second Analog-to-Digital converters, which have corresponding first and second resistor strings, comprising the steps of:
- generating a positive reference voltage;
- generating a negative reference voltage;
- disposing a global line to couple together the first resistor string and the second resistor string at a point spaced from both the positive reference voltage terminal and the negative reference voltage terminal;
- disposing a positive reference voltage line to couple together a first portion of the first resistor string and a first portion of the second resistor string, the positive reference voltage being applied to substantially a midpoint of said positive reference voltage line;
- and
- disposing a negative reference voltage line to couple together a second portion of the first resistor string and a second portion of the second resistor string, the negative reference voltage being applied substantially at a midpoint of said negative reference voltage line.
A process for operating ADC apparatus comprising the steps of:
- providing a first ADC having a first decoder, a first plurality of comparators, a first switching circuit, a first RAM, and a first resistor ladder;
- providing a second ADC having a second decoder, a second plurality of comparators, a second switching circuit, a second RAM, and a second resistor ladder;
- coupling positive voltage wiring to first ends of said first and second resistor ladders;
- coupling negative voltage wiring to second ends of said first and second resistor ladders;
- coupling a positive reference terminal to substantially a midpoint of said positive voltage wiring;
- coupling a negative voltage terminal to substantially a midpoint of said negative voltage line;
- and
- coupling a global line between said first and second resistor ladders to tend to equalize current flowing in said first and second resistor ladders.
A process of equalizing two time-interleaved ADCs, which have corresponding first, and second resistor strings, comprising the steps of:
- coupling a reference voltage line between the first and second resistor strings;
- disposing a reference voltage terminal at substantially a midpoint of said reference voltage line;
- and
- coupling a global line between the first and second resistor strings at a location spaced apart from said reference voltage line.
A method equalizing first and second Analog-to-Digital converters disposed in the read channel of a hard disk drive, the ADCs having corresponding first and second resistor strings, comprising the steps of;
- generating a positive reference voltage;
- generating a negative reference voltage;
- and
- coupling a global line in the read channel between the first resistor string and the second resistor string at a point spaced from both the positive reference voltage terminal and the negative reference voltage terminal;
- disposing a positive reference voltage line in the read channel and coupling it to a first portion of the first resistor string and a first portion of the second resistor string, the positive reference voltage being applied substantially at a midpoint of said positive reference voltage line:
- and
- disposing a negative reference voltage line in the read channel and coupling it to a second portion of the first resistor string and a second portion of the second resistor string, the negative reference voltage being applied substantially at a midpoint of said negative reference voltage line.
A process for equalizing first and second Analog-to-Digital converters, which have corresponding first and second resistor strings, comprising the steps of:
- providing a positive reference voltage;
- providing a negative reference voltage;
- coupling together the first resistor string and the second resistor string at a point spaced from where both the positive reference voltage and the negative reference voltage are provided, to cause current to flow between said resistor strings;
- coupling together a first portion of the first resistor string and a first portion of the second resistor string, the positive reference voltage being applied substantially at a midpoint of where the first portion of the first resistor string and the first portion of the second resistor string are coupled together;
- and
- coupling together a second portion of the first resistor string and a second portion of the second resistor string, the negative reference voltage being applied substantially at a midpoint of where the second portion of the first resistor string and the second portion of the second resistor string are coupled together.
A method for equalizing two time-interleaved ADCs, which have corresponding first and second resistor strings, comprising the steps of:
- coupling one end of the first resistor string to one end of the second resistor string with a conductor;
- applying a reference voltage to substantially a midpoint of a conductor coupling the first and second resistor strings;
- and
- coupling together the first and second resistor strings at a location spaced apart from where the reference voltage is applied to the first and second resistor strings.
Dependencies are inferred from the claim text.