Method and apparatus for digital-to-analog conversion with an effective pulse width modulation

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising:

• a signal generator configured to perform a pulse width modulation and to generate a pulse-width-modulated signal having a plurality of first pulses;
• an amplitude regulator configured to regulate an amplitude of said pulse-width-modulated signal generated by said signal generator;
• a bottom-level regulator configured to receive the upper nh bits of said n-bit digital data set and to regulate a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data set;
• a voltage adding circuit configured to add said pulse-width-modulated signal having an amplitude regulated by said amplitude regulator to said voltage having a bottom level regulated by said bottom-level regulator and to output a composite voltage;
• and
• a voltage smoothing circuit configured to smooth said composite voltage output by said voltage adding circuit.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising:

• a signal generator configured to perform a pulse width modulation, to generate a first pulse-width-modulated signal having a plurality of first pulses, and to generate a pulse-width-modulated (pwm) cycle signal indicating a cycle of said pulse width modulation;
• a low-weighted value manager configured to receive said first pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and to generate multi-bit pulse-width-modulated signals;
• a level regulator configured to receive said multi-bit pulse-width-modulated signals and to output an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width-modulated signals;
• and
• a voltage smoothing circuit configured to smooth said analog voltage output by said level regulator.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits, middle nm bits, and lower nl bits to an analog voltage, comprising:

• a signal generator configured to perform a pulse width modulation, to generate a first pulse-width-modulated signal having a plurality of first pulses, and to generate a pulse-width-modulated (pwm) cycle signal indicating a cycle of said pulse width modulation;
• a low-weighted value manager configured to receive said first pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and to divide a pulse width of said first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the lower nl bits of said n-bit digital data set, to add said plurality of fraction pulse widths to respective of said plurality of the first pulses, and to generate a second pulse-width-modulated signal;
• an amplitude regulator configured to regulate an amplitude of said second pulse-width-modulated signal generated by said signal generator;
• a bottom-level regulator configured to receive the upper nh bits of said n-bit digital data set and to regulate a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data set;
• a voltage adding circuit configured to add said second pulse-width-modulated signal having an amplitude regulated by said amplitude regulator to said voltage having a bottom level regulated by said bottom-level regulator and to output a composite voltage;
• and
• a voltage smoothing circuit configured to smooth said composite voltage output by said voltage adding circuit.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits, middle nm bits, and lower nl bits to an analog voltage, comprising:

• a signal generator configured to perform a pulse width modulation, to generate a first pulse-width-modulated signal having a plurality of first pulses, and to generate a pulse-width-modulation (pwm) cycle signal indicating a cycle of said pulse width modulation;
• a first low-weighted value manager configured to receive said first pulse-width-modulated signal, said pwm cycle signal, and the middle nm bits of said n-bit digital data set, and to divide a pulse width of the first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the middle nm bits of said n-bit digital data, to add said plurality of fraction pulse widths to respective of said plurality of the first pulses, and to generate a second pulse-width-modulated signal having a plurality of second pulses including said first pulse width and one of said plurality of fraction pulse widths;
• a second low-weighted value manager configured to receive said second pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and to generate multi-bit pulse-width-modulated signals including said second pulse-width-modulated signal as a least significant bit and the lower nl bits of said n-bit digital data;
• a level regulator configured to receive said multi-bit pulse-width-modulated signals and to output an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width modulated signals;
• and
• a voltage smoothing circuit configured to smooth said analog voltage output by said level regulator.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising:

• signal generating means for performing a pulse width modulation, for generating a first pulse-width-modulated signal having a plurality of first pulses, and for generating a pulse-width-modulation (pwm) cycle signal indicating a cycle of said pulse width modulation;
• low-weighted value managing means for receiving said first pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and for dividing a pulse width of the first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the lower nl bits of said n-bit digital data set, adding said plurality of fraction pulse widths to respective of said plurality of the first pulses, and generating a second pulse-width-modulated signal having a plurality of second pulses including said first pulse width and one of said plurality of fraction pulse widths;
• and
• voltage smoothing means for smoothing said second pulse-width-modulated signal output by said low-weighted value managing means.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising:

• signal generating means for performing a pulse width modulation and for generating a pulse-width-modulated signal having a plurality of first pulses;
• amplitude regulating means for regulating an amplitude of said pulse-width-modulated signal generated by said signal generating means;
• bottom-level regulating means for receiving the upper nh bits of said n-bit digital data set and regulating a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data set;
• voltage adding means for adding said pulse-width-modulated signal having an amplitude regulated by said amplitude regulating means to said voltage having a bottom level regulated by said bottom-level regulating means and outputting a composite voltage;
• and
• voltage smoothing means for smoothing said composite voltage output by said voltage adding means.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising:

• signal generating means for performing a pulse width modulation, for generating a first pulse-width-modulated signal having a plurality of first pulses, and for generating a pulse-width-modulated (pwm) cycle signal indicating a cycle of said pulse width modulation;
• low-weighted value managing means for receiving said first pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and for generating multi-bit pulse-width-modulated signals including said first pulse-width-modulated signal as a least significant bit and the lower nl bits of said n-bit digital data set;
• level regulating means for receiving said multi-bit pulse-width-modulated signals and outputting an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width-modulated signals;
• and
• voltage smoothing means for smoothing said analog voltage output by said level regulator.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits, middle nm bits, and lower nl bits to an analog voltage, comprising:

• signal generating means for performing a pulse width modulation, for generating a first pulse-width-modulated signal having a plurality of first pulses, and for generating a pulse-width-modulated (pwm) cycle signal indicating a cycle of said pulse width modulation;
• low-weighted value managing means for receiving said first pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and for dividing a pulse width of said first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the lower nl bits of said n-bit digital data set, adding said plurality of fraction pulse widths to respective of said plurality of the first pulses, and generating a second pulse-width-modulated signal having a plurality of second pulses including said first pulse width and one of said plurality of fraction pulse widths;
• amplitude regulating means for regulating an amplitude of said second pulse-width-modulated signal generated by said signal generating means;
• bottom-level regulating means for receiving the upper nh bits of said n-bit digital data and regulating a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data;
• voltage adding means for adding said second pulse-width-modulated signal having an amplitude regulated by said amplitude regulating means to said voltage having a bottom level regulated by said bottom-level regulating means and outputting a composite voltage;
• and
• voltage smoothing means for smoothing said composite voltage output by said voltage adding means.

A digital-to-analog converter for converting an n-bit digital data set including upper nh bits, middle nm bits, and lower nl bits to an analog voltage, comprising:

• signal generating means for performing a pulse width modulation, for generating a first pulse-width-modulated signal having a plurality of first pulses, and for generating a pulse-width-modulated (pwm) cycle signal indicating a cycle of said pulse width modulation;
• first low-weighted value managing means for receiving said first pulse-width-modulated signal, said pwm cycle signal, and the middle nm bits of said n-bit digital data set, and for dividing a pulse width of the first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the middle nm bits of said n-bit digital data set, adding said plurality of fraction pulse widths to respective of said plurality of the first pulses, and generating a second pulse-width-modulated signal having a plurality of second pulses having said first pulse width and one of said plurality of fraction pulse widths;
• second low-weighted value managing means for receiving said second pulse-width-modulated signal, said pwm cycle signal, and the lower nl bits of said n-bit digital data set, and for generating multi-bit pulse-width-modulated signals including said second pulse-width-modulated signal as a least significant bit and the lower nl bits of said n-bit digital data set;
• level regulating means for receiving said multi-bit pulse-width-modulated signals and outputting an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width-modulated signals;
• and
• voltage smoothing means for smoothing said analog voltage output by said level regulating means.

A method of digital-to-analog conversion for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising the steps of:

• performing a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of said n-bit digital data set;
• generating a first pulse-width-modulated signal having a plurality of first pulses including a first pulse width;
• generating a pulse-width-modulated (pwm) cycle signal indicating a cycle of a pulse width modulation performed;
• dividing a pulse width of said first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the lower nl bits of said n-bit digital data set;
• adding said plurality of fraction pulse widths to respective of said plurality of first pulses;
• outputting a second pulse-width-modulated signal having a plurality of second pulses including the first pulse width and one of said plurality of fraction pulse widths;
• and
• smoothing said second pulse-width-modulated signal output in said adding step.

A method of digital-to-analog conversion for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising the steps of:

• performing a pulse width modulation based on inputs of a reference clock signal and the lower nl bits of said n-bit digital data set;
• generating a pulse-width-modulated signal having a plurality of first pulses;
• regulating an amplitude of said pulse-width-modulated signal generated in said performing step;
• determining a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data set;
• adding said pulse-width-modulated signal having an amplitude regulated in said regulating step to said voltage having a bottom level determined in said determining step to output a composite voltage;
• and
• smoothing said composite voltage output in said adding step.

A method of digital-to-analog conversion for converting an n-bit digital data set including upper nh bits and lower nl bits to an analog voltage, comprising the steps of:

• performing a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of said n-bit digital data set;
• generating a first pulse-width-modulated signal having a plurality of first pulses;
• generating a pulse-width-modulation (pwm) cycle signal indicating a cycle of a pulse width modulation performed;
• generating multi-bit pulse-width-modulated signals including said pulse-width-modulated signal as a least significant bit and the lower nl bits of said n-bit digital data set;
• outputting an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width-modulated signals;
• and
• smoothing said analog voltage output in said outputting step.

A method of digital-to-analog conversion for converting an n-bit digital data set including upper nh bits, middle mn bits, and lower nl bits to an analog voltage, comprising the steps of:

• performing a pulse width modulation based on inputs of a reference clock signal and the middle run bits of said n-bit digital data set;
• generating a first pulse-width-modulated signal having a plurality of first pulses;
• generating a pulse-width-modulation (pwm) cycle signal indicating a cycle of a pulse width modulation performed;
• dividing a pulse width of the first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the lower nl bits of said n-bit digital data set;
• adding said plurality of fraction pulse widths to respective of said plurality of first pulses;
• generating a second pulse-width-modulated signal having a plurality of second pulses including said first pulse width and one of said plurality of fraction pulse widths;
• regulating an amplitude of said second pulse-width-modulated signal generated in said adding step;
• determining a bottom level of a voltage in accordance with a value of said upper nh bits of said n-bits digital data set;
• overlaying said second pulse-width-modulated signal having an amplitude regulated in said regulating step to said voltage having a bottom level determined in said determining step to output a composite voltage;
• and
• smoothing said composite voltage output in said overlaying step.

A method of digital-to-analog conversion for converting an n-bit digital data set including upper nh bits, middle nm bits, and lower nl bits to an analog voltage, comprising the steps of:

• performing a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of said n-bit digital data set;
• generating a first pulse-width-modulated signal having a plurality of first pulses including a first pulse width;
• dividing a pulse width of the first pulse-width-modulated signal into a plurality of fraction pulse widths in response to a value of the middle nm bits of said n-bit digital data set;
• adding said plurality of fraction pulse widths to respective of said plurality of first pulses;
• generating a second pulse-width-modulated signal having a plurality of second pulses including said first pulse width and one of said plurality of fraction pulse widths;
• generating multi-bit pulse-width-modulated signals including said second pulse-width-modulated signal as a least significant bit and the lower nl bits of said n-bit digital data set;
• outputting an analog voltage with an upper level regulated in response to a value of said multi-bit pulse-width-modulated signals;
• and
• smoothing said analog voltage output in said outputting step.