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US 6,606,045 B2Granted
Digital analog converter and electronic device using the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsMunehiro Azami, Mitsuaki Osame, Yutaka Shionoiri, Shou Nagao
Life of this patent
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Abstract
The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.
Claims54
A D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
2 more elements
A display device comprising a D/A converter circuit, the D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
2 more elements
An electronic device comprising a D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
2 more elements
A D/A converter circuit comprising:
- n capacitors wherein an i-th capacitor has a capacitance of 2i−1C where i is a natural number and C is a constant;
- an output terminal connected to the n capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- n switches connected to n capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding n capacitors.
2 more elements
An active matrix type liquid crystal display device comprising a D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
2 more elements
An active matrix type EL display device comprising a D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
2 more elements
A D/A converter circuit for converting “n” bit digital data to analog signals, comprising:
- “m” switches which are controlled by respective bits of lower “m” bits of the “n” bit digital data (“m” and “n”:
- natural numbers, “m”<“n”), and
- “n−m” switches which are controlled by respective bits of upper “n−m” bits of the “n” bit digital data;
- “m” capacitors connected to each of the “m” switches wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the m switches is 2k−1 C where C is a unit capacitance;
- “n−m” capacitors connected to each of the “n−m” switches wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor;
- and
- two reset switches;
- wherein two power sources and an offset power source are connected to said D/A converter circuit;
- each of the “m” switches and “n−m” switches selects either one of the two power sources;
- said two reset switches control charge of electric charges into the “m” capacitors and “n−m” capacitors;
- and
- analog signals are outputted, with a potential of said offset power source used as a reference potential, from a terminal commonly connected to the “n−m” capacitors.
10 more elements
A D/A converter circuit comprising:
- a lower bit circuit portion controlled by lower “m” bits of “n” bit digital data where n and m are natural numbers and n is greater than m, said lower bit circuit portion including m switches controlled by the respective lower m bits and “m” capacitors connected to said m switches, wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the m switches is 2k−1 C where C is a unit capacitance;
- an upper bit circuit portion controlled by the upper “n−m” bits of the “n” bit digital data, said upper bit circuit portion including “n−m” switches controlled by the respective “n−m” bits and “n−m” capacitors connected to said “n−m” switches, wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor which is connected between said lower bit circuit portion and said upper bit circuit portion;
- and
- two reset switches;
- wherein two power sources and an offset power source are connected to said D/A converter circuit,
- said two reset switches control charge of electric charges into the respective capacitors of said lower bit circuit portion and the respective capacitors of said upper bit circuit portion;
- said offset power source is connected to a common connection end of the respective capacitors of said upper bit circuit portion;
- each of the “m” switches of said lower bit circuit portion selects either one of said two power sources in compliance with a bit information, and controls charge and discharge of electric charges in corresponding one of the “m” capacitors;
- each of the “n−m” switches of said upper bit circuit portion selects either one of said two power sources in compliance with a bit information, and controls charge and discharge of electric charges in corresponding one of the “n−m” capacitors;
- and
- analog signals are outputted, with a potential of said offset power source used as a reference potential, from said common connection end of said upper bit circuit portion.
9 more elements
A D/A converter circuit comprising:
- a lower bit circuit portion controlled by lower “m” bits of “n” bit digital data where “n” and “m” are natural numbers and “n” is greater than “m” said lower bit circuit portion including “m” switches controlled by the lower m bits and “m” capacitors connected to said “m” switches, wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the m switches is 2k−1 C where C is a unit capacitance;
- an upper bit circuit portion controlled by the upper “n−m” bits of the “n” bit digital data, said upper bit circuit portion including “n−m” switches controlled by the respective upper “n−m” bits and “n−m” capacitors connected to said “n−m” switches, wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor connected between said lower bit circuit portion and said upper bit circuit portion wherein a capacitance of said coupling capacitor is equal to said unit capacitance;
- and
- two reset switches;
- wherein two power sources VH and VL and an offset power source VB are connected to said D/A converter circuit;
- said offset power source VB is connected to a common connection end of the respective capacitors of said upper bit circuit portion;
- and
- the output voltage VOUT outputted from said common connection end is expressed in terms of expressions (6a), (6b), (7) and (8).
6 more elements
An electronic device having an active matrix display device, said display device having a D/A converter circuit for converting “n” bit digital data to analog signals;
- wherein respective bits of said “n” bit digital data control “n” switches and control charge and discharge of electric charges in “n” capacitors connected to said “n” switches, respectively;
- and
- analog signals are outputted with an offset voltage used as a reference potential.
An electronic device having an active matrix display device, said display device having a D/A converter circuit for converting “n” bit digital data to analog signals, comprising:
- “m” switches which are controlled by respective bits of lower “m” bits of the “n” bit digital data (“m” and “n”:
- natural numbers, “m”<“n”), and
- “n−m” switches which are controlled by respective bits of upper “n−m” bits of the “n” bit digital data;
- “m” capacitors connected to each of “m” switches wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the “m” switches is 2k−1C where C is a unit capacitance;
- “n−m” capacitors connected to each of the “n−m” switches wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor;
- and
- two reset switches;
- wherein two power sources and an offset power source are connected to said D/A converter circuit;
- each of the “m” switches and the “n−m” switches selects either one of the two power sources;
- said two reset switches control charge of electric charges into the “m” capacitors and “n−m” capacitors;
- and
- analog signals are outputted, with a potential of said offset power source used as a reference potential, from a terminal commonly connected to the “n−m” capacitors.
10 more elements
An electronic device having an active matrix display device, said display device having a D/A converter circuit comprising:
- a lower bit circuit portion controlled by lower “m” bits of “n” bit digital data where n and m are natural numbers and n is greater than m, said lower bit circuit portion including m switches controlled by the respective lower m bits and “m” capacitors connected to said m switches, wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the m switches is 2k−1C where C is a unit capacitance;
- an upper bit circuit portion controlled by the upper “n−m” bits of the “n” bit digital data, said upper bit circuit portion including “n−m” switches controlled by the respective “n−m” bits and “n−m” capacitors connected to said “n−m” switches, wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor connected between said lower bit circuit portion and said upper bit circuit portion;
- and
- two reset switches;
- wherein two power sources and an offset power source are connected to said D/A conversion circuit,
- said two reset switches control charge of electric charges into the respective capacitors of said lower bit circuit portion and the respective of said upper bit circuit portion;
- said offset power source is connected to a common connection end of the respective capacitors of said upper bit circuit portion;
- each of the “m” switches of said lower bit circuit portion selects either one of said two power sources in compliance with a bit information, and controls charge and discharge of electric charges in corresponding one of the “m” capacitors;
- each of the “n−m” switches of said upper bit circuit portion selects either one of said two power sources in compliance with each bit information, and controls charge and discharge of electric charges in corresponding one of the “n−m” capacitors;
- and
- analog signals are outputted, with the potential of said offset power source used as a reference potential, from said common connection end of said upper bit circuit portion.
9 more elements
An electronic device having an active matrix display device, said display device having a D/A converter circuit comprising:
- a lower bit circuit portion controlled by lower “m” bits of “n” bit digital data where “n” and “m” are natural numbers and “n” is greater than “m”, said lower bit circuit portion including “m” switches controlled by the lower m bits and “m” capacitors connected to said switches, wherein a capacitance of one of the “m” capacitors connected to a k-th switch of the m switches is 2k−1 C where C is a unit capacitance;
- an upper bit circuit portion controlled by the upper “n−m” bits of the “n” bit digital data, said upper bit circuit portion including “n−m” switches controlled by the respective upper “n−m” bits and “n−” capacitors connected to said “n−m” switches, wherein a capacitance of one of the “n−m” switches connected to an i-th switch of the “n−m” switches is 2i−1C;
- a coupling capacitor connected between said lower bit circuit portion and said upper bit circuit portion wherein a capacitance of said coupling capacitor is equal to said unit capacitance;
- and
- two reset switches;
- wherein two power sources VH and VL and an offset power source VB are connected to said D/A converter circuit;
- said offset power source VB is connected to a common connection end of the respective capacitors of said upper bit circuit portion;
- and
- the output voltage VOUT outputted from said common connection end is expressed in terms of expressions (6a), (6b), (7) and (8).
6 more elements
A D/A converter circuit comprising
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- a load capacitor connected to the output terminal;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and second voltage sources to the corresponding capacitors.
3 more elements
A display device comprising a D/A converter circuit, the D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- a load capacitor connected to the output terminal;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and second voltage sources to the corresponding capacitors.
3 more elements
An electronic device comprising a D/A converter circuit comprising:
- a plurality of capacitors;
- an output terminal connected to the plurality of capacitors;
- a load capacitor connected to the output terminal;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
3 more elements
A D/A converter circuit comprising:
- n capacitors wherein i-th capacitor has a capacitance of 2i−1C where i is a natural number and C is a constant;
- an output terminal connected to the n capacitors;
- a load capacitor connected to the output terminal;
- an offset power source connected to the output terminal through a reset switch;
- a first voltage source and a second voltage source;
- n switches connected to n capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding n capacitors.
3 more elements
Dependencies are inferred from the claim text.