Filter structures for integrated circuit interfaces
AssigneeFormFactor, Inc.
InventorCharles A. Miller
Life of this patent
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Abstract
An interconnect system for linking integrated circuits (ICs) mounted on a surface of a printed circuit board (PCB) includes a trace positioned below the surface, one or more vias linking the trace to the surface of the PCB, and other conductors linking pads on the ICs to the vias. Impedances of the various components of the interconnect system are sized relative to one another to optimize interconnect system frequency response.
Claims34
An interconnect system for conductively linking a node of an integrated circuit mounted on an upper surface of a printed circuit board (PCB) to an external circuit, the node having first capacitance, wherein the PCB also has a lower surface, the interconnect system comprising:
- a trace formed on said PCB and vertically spaced below the upper surface of the PCB,
- a conductor having first inductance;
- and
- a via terminating at the upper surface of the PCB, the via providing a conductive path extending vertically within the PCB to the trace, the via having second capacitance and second inductance,
- wherein said conductor links the node to the via, and
- wherein the second capacitance is sized to satisfy a relationship between the second capacitance, the first inductance, the second inductance, and the first capacitance.
An interconnect system for linking a first node of a first integrated circuit (IC) mounted on an upper surface of a printed circuit board (PCB) to a second node of a second IC mounted on the upper surface of the PCB, the PCB also having a lower surface, the first node having first capacitance, the second node having second capacitance, the interconnect system comprising:
- a first via terminating at the upper surface of the PCB and providing a conductive path extending vertically within the PCB, the first via having third capacitance and third inductance;
- a second via terminating at the upper surface of the PCB and providing a conductive path extending vertically within the PCB, the second via having fourth capacitance and fourth inductance;
- a trace linking said first via to said second via, the trace formed on said PCB and vertically spaced below the upper surface of the PCB;
- a first conductor having first inductance and linking the first node to the first via,
- a second conductor having second inductance and linking the second via to the second node, and
- wherein sizes of the third and fourth capacitances are chosen to satisfy a relationship between the first, second, third and fourth capacitances, and the first, second, third and fourth inductances.
A method for linking a node of an integrated circuit mounted on an upper surface of a printed circuit board (PCB) to an external circuit, the node having first capacitance, wherein the PCB also has a lower surface, the method comprising the steps of:
- a. forming a trace on the PCB vertically spaced below the upper surface of the PCB,
- b. providing a conductor having first inductance;
- and
- c. designing and providing a via terminating at the upper surface of the PCB and providing a conductive path extending vertically within the PCB to the trace, the via having second capacitance and second inductance,
- wherein said conductor links the node to the via, and
- wherein size of the second capacitance is selected in relation to the first capacitance, the first inductance and the second inductance when designing the via at step c.
A method for linking a first node of a first integrated circuit (IC) mounted on an upper surface of a printed circuit board (PCB) to a second node of a second IC mounted on the upper surface of the PCB, the first node having first capacitance, the second node having second capacitance, the PCB also having a lower surface, the method comprising the steps of:
- a. designing and providing a first via terminating at the upper surface of the PCB and providing a conductive path extending vertically within the PCB, the first via having third capacitance and second inductance;
- b. designing and providing a second via terminating at the upper surface of the PCB and providing a conductive path extending vertically within the PCB, the second via having fourth capacitance and third inductance;
- c. providing a trace vertically spaced below the upper surface of the PCB, the trace linking the first and second vias;
- d. providing a first conductor having first inductance and linking the first node to the first via;
- and
- e. providing a second conductor having fourth inductance and linking the second via to the second node,
- wherein the third and fourth capacitances are sized to satisfy a relationship between the first, second, third and fourth capacitances, and the first, second, third and fourth inductances.
Dependencies are inferred from the claim text.