High-speed current-mirror circuitry and method of operating the same
AssigneeNational Semiconductor Corporation
InventorsRamsin M. Ziazadeh, Jitendra Mohan, Devnath Varadarajan, Vjay Ceekala
Life of this patent
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Abstract
There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
Claims20
An impedance-peaking current mirror comprising:
- a N-channel drive transistor having a source coupled to ground, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a N-channel mirror transistor having a source coupled to ground, a gate coupled to said drain of said N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
An amplifier having a plurality of amplification stages, at least one of said amplification stages having an impedance-peaking current mirror comprising:
- a N-channel drive transistor having a source coupled to ground, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a N-channel mirror transistor having a source coupled to ground, a gate coupled to said drain of said N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
A receiver comprising:
- a receiver front-end circuit capable of receiving an incoming information signal from an antenna;
- and
- an amplifier, associated with said receiver front-end circuit, having a plurality of amplification stages, at least one of said amplification stages having an impedance-peaking current mirror comprising:
- a N-channel drive transistor having a source coupled to ground, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a N-channel mirror transistor having a source coupled to ground, a gate coupled to said drain of said N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
A method of operating an impedance-peaking current mirror, said impedance-peaking current mirror comprising (i) N-channel drive transistor having a source coupled to ground, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor, and (ii) a N-channel mirror transistor having a source coupled to ground, a gate coupled to said drain of said N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load, said method of operation comprising the step of operating said impedance-peaking current mirror at a sufficiently high frequency to increase the impedance of said inductor thereby isolating the gate to source capacitance of said drive transistor from the gate to source capacitance of said mirror transistor at relatively high frequencies.
An impedance-peaking current mirror comprising:
- a P-channel drive transistor having a source coupled to a positive power supply, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a P-channel mirror transistor having a source coupled to said positive power supply, a gate coupled to said drain of said P-channel drive transistor, and a drain coupled to ground via an impedance load.
An amplifier having a plurality of amplification stages, at least one of said amplification stages having an impedance-peaking current mirror comprising:
- a P-channel drive transistor having a source coupled to a positive power supply, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a P-channel mirror transistor having a source coupled to said positive power supply, a gate coupled to said drain of said P-channel drive transistor, and a drain coupled to ground via an impedance load.
A receiver comprising:
- a receiver front-end circuit capable of receiving an incoming information signal from an antenna;
- and
- an amplifier, associated with said receiver front-end circuit, having a plurality of amplification stages, at least one of said amplification stages having an impedance-peaking current mirror comprising:
- a P-channel drive transistor having a source coupled to a positive power supply, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor;
- and
- a P-channel mirror transistor having a source coupled to said positive power supply, a gate coupled to said drain of said P-channel drive transistor, and a drain coupled to ground via an impedance load.
A method of operating an impedance-peaking current mirror, said impedance-peaking current mirror comprising (i) a P-channel drive transistor having a source coupled to a positive power supply, a drain coupled to a current source and a gate coupled to said drain via a series connection of a resistor and an inductor, and (ii) a P-channel mirror transistor having a source coupled to said positive power supply, a gate coupled to said drain of said P-channel drive transistor, and a drain coupled to ground via an impedance load, said method of operation comprising the step of operating said impedance-peaking current mirror at a sufficiently high frequency to increase the impedance of said inductor thereby isolating the gate to source capacitance of said drive transistor from the gate to source capacitance of said mirror transistor at relatively high frequencies.
Dependencies are inferred from the claim text.