Voltage conversion circuit

A voltage conversion circuit comprising:

• an input node for receiving an input DC voltage;
• a first output node and a second output node;
• a plurality of MOS transistors;
• a plurality of capacitive devices for storing and transferring charge;
• said plurality of MOS transistors forming a switching network for routing charge among said plurality of capacitive devices to produce a predetermined positive voltage at said first output node and a predetermined negative voltage at said second output node, said switching network including first PMOS transistors and first NMOS transistors for producing said predetermined positive voltage at said first output node, and including at least one second NMOS transistor for producing said negative voltage at said second output node;
• wherein:
• at least one of said first NMOS transistors is formed directly in a p-type active layer of a semiconductor substrate, and said semiconductor substrate further has a first n-well and a second n-well of n-type conductivity in said p-type active layer;
• said first PMOS transistors are formed in said first n-well;
• and
• at least one of said first NMOS transistors and said second NMOS transistor are formed in a first p-well of p-type conductivity formed in said second n-well.

A voltage conversion circuit comprising:

• an input node for receiving an input DC voltage;
• a first output node and a second output node;
• a plurality of MOS transistors;
• a plurality of capacitive devices for storing and transferring charge;
• said plurality of MOS transistors forming a switching network for routing charge among said plurality of capacitive devices to produce a predetermined positive voltage at said first output node and a predetermined negative voltage at said second output node, said switching network including first PMOS transistors and first NMOS transistors for producing said predetermined positive voltage at said first output node, and including second PMOS transistors and second NMOS transistors for producing said negative voltage at said second output node;
• wherein:
• the second NMOS transistors are formed directly in a p-type active layer of a semiconductor substrate, and said semiconductor substrate further has a first n-well and a second n-well of n-type conductivity in said p-type active layer;
• the first PMOS transistors and the second PMOS transistors are formed in said first n-well;
• and
• the first NMOS transistors are formed in a first p-well of p-type conductivity formed in said second n-well.

A voltage conversion circuit comprising:

• an input node for receiving an input DC voltage;
• a first output node and a second output node;
• a plurality of MOS transistors;
• a plurality of capacitive devices for storing and transferring charge;
• said plurality of MOS transistors forming a switching network for routing charge among said plurality of capacitive devices to produce a predetermined positive voltage at said first output node and a predetermined negative voltage at said second output node, said switching network including at least one first PMOS transistor for producing said positive voltage at said first output node, and including second PMOS transistors and second NMOS transistors for producing said predetermined negative voltage at said second output node;
• wherein:
• said second PMOS transistors are formed directly in an n-type active layer of a semiconductor substrate, and said semiconductor substrate further has a first p-well and a second p-well of p-type conductivity in said n-type active layer;
• said second NMOS transistors are formed in first p-well;
• said first PMOS transistor is formed in a first n-well of n-type conductivity formed in said second n-well.

A voltage conversion circuit comprising:

• an input node for receiving an input DC voltage;
• a first output node and a second output node;
• a booster circuit for boosting said input DC voltage by a factor of n and outputting the boosted voltage as a positive voltage at said first output node;
• a capacitive device;
• a plurality of MOS transistors forming a switching network for transferring charge from said booster circuit to said capacitive device, the resultant voltage across said capacitive device being output as a negative voltage at said second output node, said switching network including PMOS and NMOS transistors used in the generation of the negative voltage across said capacitive device;
• wherein
• a first group of said NMOS transistors are formed in a p-type active layer of a semiconductor substrate, and said semiconductor substrate further has a first n-well and a second n-well of n-type conductivity in said p-type active layer;
• said PMOS transistors are formed in said first n-well;
• a second group of said NMOS transistors are formed in a first p-well of p-type conductivity formed in said second n-well.