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US 6,605,978 B1Granted
Method of forming a voltage detection device and structure therefor
AssigneeSemiconductor Components Industries, LLC
InventorsJosef Halamik, Frantisek Sukup
Life of this patent
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Abstract
A voltage detection device (10, 30) utilizes grounded gate J-FET transistors (16,17,18) to detect desired input voltage values. The grounded gate J-FET transistors (16,17,18) function in different modes as the input voltage varies to facilitate detecting the desired input voltage values.
Claims16
A method of forming a voltage detection device comprising:
- forming a plurality of J-FET transistors coupled to receive an input voltage and responsively operate in a triode mode when the input voltage is less than a first value and to operate in a drain current saturation mode when the input voltage is greater than a second value;
- forming a first J-FET transistor of the plurality of J-FET transistors to operate in a pinch-off mode when the input voltage is greater than the first value and less than the second value;
- and
- forming a first MOS transistor to receive a voltage of a first current carrying electrode of a second J-FET transistor of the plurality of J-FET transistors and to responsively couple a control electrode of a second MOS transistor to the input voltage.
1 more element
A method of forming a voltage detection device comprising:
- coupling an output of the voltage detection device to follow an input voltage when the input voltage is less than a first value;
- clamping the output to a first output voltage value when the input voltage is at least equal to the first value and less than a second value by operating a first grounded gate J-FET transistor in a pinch-off mode;
- and
- coupling the output to a second output voltage value when the input voltage is at least equal to the second value by operating the first grounded gate J-FET transistor in a drain current saturation mode.
1 more element
A voltage detection device comprising:
- a first grounded gate J-FET transistor having a first current carrying electrode coupled to a voltage input, a control electrode coupled to a voltage return, and a second current carrying electrode;
- a second grounded gate J-FET transistor having a first current carrying electrode coupled to the second current carrying electrode of the first grounded gate J-FET transistor, a control electrode coupled to the voltage return and a second current carrying electrode;
- a first transistor having a first current carrying electrode coupled to the voltage input, a control electrode coupled to the second current carrying electrode of the first grounded gate J-FET transistor, and a second current carrying electrode;
- and
- a second transistor having a first current carrying electrode coupled to the second current carrying electrode of the second grounded gate J-FET transistor, a control electrode coupled to the second current carrying electrode of the first transistor, and a second current carrying electrode coupled to the voltage return.
2 more elements
Dependencies are inferred from the claim text.