High voltage discharge circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYue-der Chih
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Abstract
This invention provides a circuit and a method for discharging a high voltage to ground level from a circuit node especially in intergrated circuits. The invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process. In addition, the discharge process takes a short amount of time. A feedback mechanism from the drains of the FETs through inverters back to gate #2 of the dual-gated FETs causes the individual drains of series connected FETs to discharge rapidly. The discharge mechanism of this invention minimizes the voltage times current power and therefore protects the integrated devices from damage.
Claims26
A high voltage discharge circuit comprising:
- a dual-gate element having a first and second NMOS transistor each said transistor having gate, drain, and source wherein said drains and said first gate are commonly coupled to a first node and wherein said sources are commonly coupled,
- an inverter having its input coupled to said first node and output coupled to said second gate, and
- a current source between said commonly coupled sources and a second node wherein said circuit is capable of discharging a high voltage or said first node through said second node.
A high voltage discharge circuit comprising:
- a bias FET which discharges four series connected dual-gated FETs to ground, wherein said four series connected dual-gated FETs have an inverter connected from said FETs' drain to one of said FETs' gates and wherein said four series connected dual-gated FETs cause a high voltage node to discharge quickly and wherein the drain to source voltages on said four series connected dual-gated FETs are kept low during the discharge operation preventing device damage.
A method of discharging high voltage from an internal node of an integrated circuit comprising the steps of:
- connecting a dual-gate element having a first and second NMOS transistor each said transistor having gate, drain, and source wherein said drains and said first gate are commonly coupled to a first node and wherein said sources are commonly coupled,
- connecting an inverter having its input coupled to said first node and output coupled to said second gate, and
- connecting a current source between said commonly coupled sources and a second node wherein said circuit is capable of discharging a high voltage or said first node through said second node.
Dependencies are inferred from the claim text.