Integrated circuit with switched capacitor network for recycling power
AssigneeLSI Logic Corporation
InventorBradley J. Wright
Life of this patent
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Abstract
A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.
Claims20
An integrated circuit clock network comprising:
- a clock network having at least one clock net, including a first clock net;
- a clock driver having a clock output coupled to the first clock net;
- and
- a switched capacitor network comprising a plurality of capacitors selectively decoupled from the clock network, selectively coupled to the first clock net in parallel with one another, and selectively coupled to at least one of the clock nets in series with one another.
An integrated circuit comprising:
- a plurality of nets, including a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit;
- and
- a switched capacitor network comprising a plurality of capacitors selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.
A method of recycling power in an integrated circuit having a plurality of nets, the method comprising:
- (a) repetitively switching a first of the nets on the integrated circuit between logic high and low states during normal operation of the integrated circuit;
- (b) temporarily coupling a plurality of capacitors to the first net in parallel with one another when the first net is in the logic high state and then decoupling the plurality of capacitors from the first net while the first net is still in the logic high state;
- and
- (c) temporarily coupling the plurality of capacitors in series with one another to at least one of the nets, after step (b).
Dependencies are inferred from the claim text.