Method and apparatus for crossing from an unstable to a stable clock domain in a memory device

A method of operating a memory device comprising:

• receiving a first external clock signal and using said external clock signal to latch incoming data on a data path;
• receiving a second external clock signal and generating a master clock signal therefrom;
• using said master clock signal to generate a control signal;
• and
• enabling a receiver which receives said first external clock signal with a first enable signal which is derived from said control signal, a plurality of clock signals derived from said second external clock signal, said master clock signal and said first and second external clock signals.

A method of operating a memory device comprising:

• generating a master clock signal from a first external clock signal;
• generating a plurality of second clock signals from said first external clock signal, said plurality of second clock signals being phase shifted from one another;
• generating a first enable signal with an edge of said master clock signal;
• associating said edge of said master clock signal which generated said first enable signal with one of said plurality of second clock signals which has a clock pulse which envelopes said edge;
• using an edge of said clock pulse of said one second clock signal to generate a second enable signal;
• and
• using said second enable signal to enable a receiver which receives a second external signal.

A memory device comprising:

• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• and
• a logic circuit which associates a plurality of successive edges of said first internal clock signal with a respective one of said N clock signals and determines which one of said N clock signals is associated with the clock edge of said first internal clock used to generate said first control signal, said logic circuit generating a first receiver enable signal from said determined one of said N clock signals and also from said first control signal.

A memory device comprising:

• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• a logic circuit responsive to said first control signal, said first external clock signal, said first internal clock signal, and said N second clock signals for associating an edge of said internal clock signal which generated said first control signal with one of said N clock signals;
• and
• a selectively enabled receiver which is responsive to said first receiver enabling signal to permit signal input into said memory device.

A memory device comprising:

• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• a logic circuit for receiving said first control signal and which associates an edge of said first internal clock signal which generated said first control signal with one of said plurality of second clock signals which has a clock pulse which envelopes said edge and uses an edge of said clock pulse to generate a receiver enable signal.

A processor system comprising:

• a processor;
• and
• a memory device coupled to said processor, said memory device comprising:
• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• and
• a logic circuit which associates a plurality of successive edges of said first internal clock signal with a respective one of said N clock signals and determines which one of said N clock signals is associated with the clock edge of said first internal clock used to generate said first control signal, said logic circuit generating a first receiver enable signal from said determined one of said N clock signals and also from said first control signal.

A processor system comprising:

• a processor;
• and
• a memory device coupled to said processor;
• said memory device comprising:
• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• a logic circuit responsive to said first control signal, said first external clock signal, said first internal clock signal, and said N second clock signals for associating an edge of said internal clock signal which generated said first control signal with one of said N clock signals;
• and
• a selectively enabled receiver which is responsive to said first receiver enabling signal to permit signal input into said memory device.

A processor system comprising:

• a processor;
• and
• a memory device coupled to said processor;
• said memory device comprising:
• a first signal generator which generates a first internal clock signal from a first external clock signal which has a frequency fc;
• a second signal generator which generates a first control signal from an edge of said internal clock signal;
• a third signal generator which generates N second clock signals from said first external clock signal, each of said N second clock signals having a frequency of fc/N and being phase shifted relative to each other, where N> 1;
• a logic circuit for receiving said first control signal and which associates an edge of said first internal clock signal which generated said first control signal with one of said plurality of second clock signals which has a clock pulse which envelopes said edge and uses an edge of said clock pulse to generate a receiver enable signal.