Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers

A delay-locked loop, comprising:

• a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• a comparison circuit coupled to the variable delay line and configured to receive the input clock signal, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals;
• and
• a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

A delay-locked loop, comprising:

• an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal;
• a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• a mode delay line adapted to receive a output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state;
• a feedback delay line coupled to the mode delay line and operable to generate a feedback clock signal responsive to the mode delayed clock signal, the feedback clock signal having a model delay relative to the mode delayed clock signal;
• a comparison circuit coupled to the input buffer and coupled to the feedback delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the buffered and feedback clock signals;
• and
• an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

A delay-locked loop, comprising:

• an input buffer configured to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal;
• a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and buffered clock signals;
• a mode delay line configured to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a first mode delay relative to the delayed clock signal responsive to the output drive strength signal having a first logic state and having a second mode delay responsive to the output drive strength signal having a second logic state;
• and
• an output buffer coupled to the variable delay line and operable in a full-drive mode responsive to the output drive strength signal having the first logic state to generate a first synchronized output signal in response to the delayed clock signal, and operable in a reduced-drive mode responsive to the output drive strength signal having the second logic state to generate a second synchronized output signal in response to the delayed clock signal.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a delay-locked loop coupled to at least the read/write circuit and being adapted to receive an input clock signal, the delay-locked loop comprising,
• a variable delay line configured to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• a comparison circuit coupled to the variable delay line, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed and input clock signals;
• and
• a mode delay line adapted to receive an output drive strength signal and coupled to the variable delay line, the mode delay line generating a mode delayed clock signal having a mode delay relative to the delayed clock signal and the mode delay being a function of the output drive strength signal.

A method of adjusting a delay of a delayed clock signal relative to an applied clock signal in a delay-locked loop, the method comprising:

• generating the delayed clock signal having a delay relative to the applied clock signal;
• delaying the delayed clock signal by a feedback delay to generate a feedback clock signal;
• detecting a phase difference between the delayed clock signal and the feedback clock signal;
• adjusting the delay of the delayed clock signal in response to the detected phase difference;
• detecting a state of an output drive strength bit, the bit having a plurality of states and each state corresponding to a drive-strength mode of the data signals;
• and
• adjusting the feedback delay in response to the detected state of the output drive strength bit.

A method of adjusting a delay of a delayed clock signal relative to an applied clock signal in a delay-locked loop, the method comprising:

• generating the delayed clock signal having a delay relative to the applied clock signal;
• detecting a phase difference between the delayed clock signal and the applied clock signal;
• adjusting the delay of the delayed clock signal in response to the detected phase difference;
• generating a synchronized clock signal in response to the delayed clock signal, the synchronized clock signal having a delay relative to the delayed clock signal;
• detecting a state of an output drive strength bit, the bit having a plurality of states and each state corresponding to a drive-strength mode of the data signals;
• and
• adjusting the delay of the synchronized clock signal in response to the detected state of the output drive strength bit.