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US 6,605,962 B2Granted
PLD architecture for flexible placement of IP function blocks
AssigneeAltera Corporation
InventorsAndy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
Life of this patent
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Abstract
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
Claims20
A programmable logic device (PLD), comprising:
- a plurality of logic elements (LE's) arranged in an array;
- a base signal routing architecture including a plurality of signal routing lines to route signals among the LE's,
- wherein
- a hole is formed in the array of LE's, and the hole is characterized by a perimeter portion and a central portion;
- the base signal routing architecture is, at least in part, interrupted at the hole;
- and
- the PLD further comprises interface circuitry within the perimeter portion of the hole, configurable to couple circuitry within the hole to the signal routing architecture;
- and
- the PLD further comprises an IP function block within the hole and electrically coupled to the interface circuitry.
6 more elements
A programmable logic device (PLD), comprising:
- a plurality of logic elements (LE's) arranged in an array;
- a base signal routing architecture including a plurality of signal routing lines to route signals among the LE's, the signal routing lines including short lines and long lines, at least one IP function block inserted into the array in place of a portion of the LE's, wherein a first subset of the short lines connect to the IP function block and second subset of the short lines terminate at the IP function block while at least one long line passes by the IP function block.
A semiconductor integrated circuit, comprising:
- a plurality of logic elements (LE's) arranged in an array with at least one IP function block inserted into the array.
- a base signal routing architecture connected to the LE's and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is terminated at the IP function block and a second portion of the base signal routing architecture continues past the IP function block.
Dependencies are inferred from the claim text.