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US 6,605,961 B1Granted
Low voltage PLA's with ultrathin tunnel oxides
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
Systems and methods for programmable logic arrays having depletion mode, non volatile p-channel floating gate transistors with ultra thin tunnel oxides are provided. The programmable logic arrays of the present invention can be programmed with voltages of 2.0 to 3.0 Volts and the normal operating voltages on the control gates are of the order 1.0 Volt. The depletion mode, non volatile p-channel floating gate transistors the present invention, include a range of floating gate potentials over which charge can not leak on to or off of the floating gate. The non volatile p-channel floating gate transistors in the programmable logic array include an oxide layer of less than 50 Angstroms (Å) which separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.
Claims59
A programmable logic array, comprising:
- a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
- a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
- and
- wherein the non-volatile memory cells each include a depletion mode p-channel memory cell, comprising:
- a control gate;
- a floating gate separated from the control gate by a dielectric layer, the floating gate including heavily doped silicon of one predominant carrier type;
- and
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.
5 more elements
A low voltage programmable logic array with ultra thin tunnel gate oxides, comprising:
- a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
- a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
- and
- wherein the non-volatile memory cells each include a depletion mode p-channel static device, comprising:
- a source region;
- a drain region;
- a channel region between the source and drain regions;
- a floating gate including heavily doped silicon of one predominant carrier type;
- and
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from the channel region.
7 more elements
A programmable logic array, comprising:
- a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
- a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
- and
- wherein the non-volatile memory cells each include a depletion mode p-channel floating gate transistor, comprising:
- a source region;
- a drain region;
- a channel region between the source and drain regions;
- a floating gate;
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from the channel region;
- and
- wherein the transistor has a limited range of floating gate potentials or electron energies for which electrons can neither tunnel to the channel region or the source region nor electrons tunnel from the channel region or the source region to the floating gate.
8 more elements
A programmable logic array, comprising:
- a plurality of input lines for receiving an input signal;
- a plurality of output lines;
- and
- one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes a depletion mode p-channel floating gate transistor, comprising:
- a control gate;
- a floating gate separated from the control gate by a dielectric layer, the floating gate including heavily doped silicon of one predominant carrier type;
- and
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.
5 more elements
A programmable logic array, comprising:
- a plurality of input lines for receiving an input signal;
- a plurality of output lines;
- and
- one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes a depletion mode p-channel floating gate transistor, comprising:
- a control gate;
- a floating gate separated from the control gate by a dielectric layer;
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate and
- wherein the transistor has a limited range of floating gate potentials or electron energies for which electrons can neither tunnel to the channel region or the source region nor electrons tunnel from the channel region or the source region to the floating gate.
5 more elements
An electronic system, the electronic system comprising a programmable logic array, the programmable logic array including:
- a plurality of input lines for receiving an input signal;
- a plurality of output lines;
- and
- one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes a depletion mode p-channel floating gate transistor, comprising:
- a control gate;
- a floating gate separated from the control gate by a dielectric layer;
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate and
- wherein the transistor has a limited range of floating gate potentials or electron energies for which electrons can neither tunnel to the channel region or the source region nor electrons tunnel from the channel region or the source region to the floating gate.
5 more elements
An electronic system, comprising:
- a memory;
- a processor coupled to the memory;
- and
- wherein the processor includes at least one programmable logic array including:
- a plurality of input lines for receiving an input signal;
- a plurality of output lines;
- and
- one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes a depletion mode p-channel floating gate transistor, comprising:
- a control gate;
- a floating gate separated from the control gate by a dielectric layer;
- an oxide layer of less than 50 Angstroms (Å), wherein the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate and
- wherein the transistor has a limited range of floating gate potentials or electron energies for which electrons can neither tunnel to the channel region or the source region nor electrons tunnel from the channel region or the source region to the floating gate.
9 more elements
A method for forming a programmable logic array, comprising:
- forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
- forming a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
- and
- wherein forming the non-volatile memory cells includes forming depletion mode p-channel memory cell, forming the depletion mode p-channel memory cells, comprising:
- forming a control gate;
- forming a floating gate separated from the control gate by a dielectric layer, the floating gate including heavily doped silicon of one predominant carrier type;
- and
- forming an oxide layer of less than 50 Angstroms (Å), wherein forming the oxide layer separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.
5 more elements
A method for operating a programmable logic array comprising operating a programmable logic array having a number of non volatile depletion mode, floating gate, p-channel memory cells with ultra thin gate oxides, further comprising:
- selectively storing a limited charge on at least one of the floating gates for the number of non volatile depletion mode, floating gate, p-channel memory cells, wherein selectively storing the limited charge on the at least one of the floating gates controls an electrical conduction between a source and a drain region for that non volatile depletion mode, floating gate, p-channel memory cell;
- and
- applying a limited range of floating gate potentials to the number of non volatile depletion mode, floating gate, p-channel memory cells in the array.
Dependencies are inferred from the claim text.