Programmable logic configuration device with configuration memory accessible to a second device

#The present invention relates to configuration devices used to program devices such as a programmable logic devices or other similar devices.

#Programmable logic devices (“PLDs”) (also sometimes referred to as PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, or FPGAs), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to not necessarily exclude such devices.

#In some implementations, a PLD is programmed by the system processor, the system processor being any circuitry primarily responsible for interacting with memory and I/O devices to execute instructions for carrying out system tasks.

#The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several aspects of particular embodiments of the invention are described by reference to the following figures.

#FIG. 1 illustrates an embodiment of an implementation of the present invention in which a system processor accesses a memory of a PLD configuration device also accessed by a controller of the PLD configuration device.

#FIG. 2 illustrates another embodiment of the present invention in which a PLD accesses a memory of a PLD configuration device also accessed by a controller of the PLD configuration device.

#The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of particular applications and their requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

#FIG. 1 shows an electronic system (i.e. any system involving electrical or electromagnetic signals) 10 in which an embodiment of the present invention may be implemented. System 10 includes a processor 11, a programmable logic device (PLD) 12, and a PLD configuration device 13. PLD configuration device 13 includes a memory 13a and a controller 13b. In the present embodiment, configuration device 13 is implemented as a single package. Memory 13a may be implemented, for example, as a non-volatile memory chip such as a 16 megabit flash memory chip. Controller 13b may be implemented as a controller chip operatively coupled to the 16 megabit flash memory chip serving as memory 13a. As one possible alternative, memory 13a and controller 13b might be implemented on a single chip with a first portion of the chip serving as memory 13a and a second portion of the chip serving as controller 13b.

#PLD configuration controller 13b is connectable to PLD 12 via pins P-C-1. PLD configuration controller 13b is operatively coupled to memory 13a via bus line B-1. Bus line B-1 is also accessible for connection with processor 11 via pins P-B-1 so that processor 11 may also access memory 13a. Pins P-B-1 comprise one or more pins for connecting a conductive path or paths between bus B-1 and processor 11-1. The term “pins” as used herein includes conductive paths from one device for connection to another device. “Pins” as used herein may refer to one or more male connector heads for insertion into a female connector, or for soldering to a circuit board, to complete a conductive path or paths between devices. However, the term pins as used herein has a broader definition and may therefore also simply refer to a conductive path (or paths) itself, whether or not the conductive path is capable of being readily disconnected and reconnected through, for example, male and female complementary connectors. Thus, where a conductive path exists between two devices and whether or not that path is readily disconnectable and re-connectable, the first device may be said to be operatively coupled to “pins” connectable to the second device. Controller 13b is also operatively coupled to pins P-D-1a and pins P-D-1b for connection to processor 13 over dedicated lines D-1a and D-1b.