Structure and method for implementing wide multiplexers
AssigneeLattice Semiconductor Corporation
InventorsDouglas C. Morse, Clement Lee
Life of this patent
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Abstract
A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding multiplexer with less number of input signals. In one embodiment, each of a number of 8-input multiplexers shares both common input signals and common selection signals with a neighboring multiplexer. Even wider multiplexers can be achieved by cascading the multiplexers in a conventional manner.
Claims19
A programmable logic circuit comprising:
- a first multiplexer configured to select from a first set of M input signals to provide an output signal;
- a second multiplexer configured to select from a second set of M input signals to provide an output signal, wherein N of the M input signals in the first and second set of input signals are the same, wherein each of the first and second multiplexers receives P selection signals, wherein Q of the P signals are received at both the first and second multiplexers;
- and
- a routing resource configured to receive the output signals from the first and second multiplexers and to select from these output signals and a routing set of input signals to provide the first and second set of M input signals.
A method for providing multiplexers in a programmable logic circuit, the method comprising:
- providing a first multiplexer and a second multiplexer, each of the first and second multiplexers receiving M input signals, wherein N of the M input signals are received at both the first and second multiplexers;
- routing the set of M input signals to each of the first and second multiplexers through a routing resource;
- routing an output signal from each of the first and second multiplexers through the routing resource as input signals to the first and second multiplexers;
- and
- providing each of the first and second multiplexers P selection signals, wherein Q of the P signals are received at both the first and second multiplexers.
A programmable logic device comprising:
- a routing resource having a first set of routing input lines and a second set of routing input lines, each routing input set including at least two data lines and one or more control lines;
- a first multiplexer having input terminals coupled to the data lines of the first routing input set and at least two data lines of the second routing input set, and having select terminals coupled to the one or more control lines of the first routing input set and to a control line of the second routing input set;
- and
- a second multiplexer coupled to the second set of routing input lines, the first multiplexer being configurable to select among the data lines of the first routing input set in one configuration and among the data lines of the first and second routing input sets in another configuration.
A method for implementing a 2M:1 multiplexer, comprising:
- providing a first, second, third, and a fourth M:1 multiplexer, wherein the first and second M:1 multiplexers share a first set of N input signals, the second and third M:1 multiplexers share a second set of N input signals, and the third and fourth multiplexers share a third set of N input signals, and wherein N is less than M;
- routing a set of M input signals to the first M:1 multiplexer;
- selecting from the set of M input signals received at the first M:1 multiplexer to provide a first output signal;
- routing a set of M input signals to the fourth M:1 multiplexer;
- selecting from the set of M input signals received at the fourth M:1 multiplexer to provide a second output signal;
- routing the first and second output signal into the second set of N input signals received at the third M:1 multiplexer;
- and
- selecting either the first or second output signal from the second set of N input signals received at the third multiplexer M:1 to provide an third output signal, whereby the third M:1 multiplexer implements a 2M:1 multiplexer.
Dependencies are inferred from the claim text.