Semiconductor chip package and connection structure including a ground metal plane having blank patterns

An electrical connection structure for electrically connecting a semiconductor chip to an external circuit device, comprising:

• a ground conductive plate connected to ground power of the semiconductor chip;
• an insulating layer formed on the ground conductive plate;
• and
• a signal pattern layer formed on the insulating layer and having signal patterns communicating electrical signals with the semiconductor chip,
• wherein said signal pattern layer includes a chip connection portion electrically connected to the semiconductor chip, and a pattern line portion for electrically connecting the chip connection portion and external connection portion, and wherein said ground conductive plate includes an opening with a shape that corresponds to at least one of the chip connection portion, the external connection portion and the pattern line portion.

A wafer level package comprising:

• a semiconductor chip having an active surface with an on-chip circuit and electrode pads;
• and
• an electrical connection structure for electrically connecting the semiconductor chip to an external circuit device, comprising:
• a ground conductive plate connected to ground power of the semiconductor chip;
• an insulating layer formed on the ground conductive plate;
• and
• a signal pattern layer formed on the insulating layer and having signal patterns in electrical communication with the semiconductor chip,
• wherein said ground conductive plate includes an opening that corresponds to the signal pattern layer.

A wafer level package comprising:

• a semiconductor chip having an active surface with an on-chip circuit and electrode pads;
• and
• an electrical connection structure for electrically connecting the semiconductor chip to an external circuit device, comprising:
• a ground conductive plate connected to ground power of the semiconductor chip;
• an insulating layer formed on the ground conductive plate;
• and
• a signal pattern layer formed on the insulating layer and having signal patterns communicating electrical signals with the semiconductor chip,
• wherein said signal pattern layer includes a chip connection portion electrically connected to the semiconductor chip, and a pattern line portion for electrically connecting the chip connection portion and the external connection portion, and wherein said ground conductive plate includes an opening with a shape corresponds to at least one of the chip connection portion, the external connection portion and the pattern line portion.