CVD plasma process to fill contact hole in damascene process
AssigneeAdvanced Micro Devices, Inc.
InventorsBhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Christopher F. Lyons, Sanjay K. Yedur, Ramkumar Subramanian
Life of this patent
Estimating the term…
Abstract
The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
Claims11
A dual damascene structure, comprising:
- an insulating material comprising an upper portion and a lower portion;
- a via formation in the lower portion of the insulating material;
- a protective layer covering at least sidewalls of the via formation;
- and
- a conductive line trench formation in the upper portion of the insulating material.
A dual damascene structure, comprising:
- an insulating material comprising an upper portion and a lower portion;
- a via formation in the lower portion of the insulating material;
- and
- means for protecting at least edges and sidewalls of the via formation from an etch step to form a conductive line trench formation in the upper portion of the insulating material.
A dual damascene structure, comprising:
- an insulating material including at least one of silicon oxide, silicon dioxide, silicon nitride (Si3N4), (SiN), silicon oxynitride, (SiOxNy), fluonated silicon oxide (SiOxFy), and polyimide(s);
- a via formed in the insulating material;
- a protective layer formed to be conformal to at least edges and sidewalls of the via;
- and
- a conductive line trench formed above at least a portion of the via.
Dependencies are inferred from the claim text.