A scalable multi-bit flash memory cell array, comprising:
- a semiconductor substrate of a first conductivity type;
- a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active-regions being formed on said semiconductor substrate, wherein each of the plurality of parallel STI regions is filled with a raised field-oxide layer;
- a plurality of gate regions being formed alternately on said semiconductor substrate and transversely to the plurality of parallel STI regions, wherein each of the plurality of gate regions is formed between a pair of common bit-line regions and is defined by a masking photoresist step and is therefore scalable;
- a plurality of common-diffusion regions of a second conductivity type being formed in said semiconductor substrate of the plurality of active regions in said common bit-line regions;
- a flat bed being formed in each of said common bit-line regions, wherein said flat bed is formed alternately by the plurality of common-diffusion regions and etched raised field-oxide layers;
- a sidewall-oxide spacer being formed over the sidewalls of each of the plurality of gate regions and on a portion of said flat bed;
- a conductive layer acting as a bit line being formed over said flat bed between a pair of said sidewall-oxide spacers;
- a planarized thick-oxide layer being formed over a pair of said sidewall-oxide spacers and said conductive layer formed therebetween;
- two stack-gate regions being formed in the side portions of each of the plurality of gate regions and one select-gate region being formed between said two stack-gate regions, wherein each of said stack-gate regions comprises from top to bottom a sidewall-dielectric spacer formed over a sidewall created by said sidewall-oxide spacer and said planarized thick-oxide layer, an elongated control-gate layer over an intergate-dielectric layer, a plurality of integrated floating-gate layers formed under said intergate-dielectric layer;
- wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed on a thin tunneling-dielectric layer and two extended floating-gate layers being separately formed on a portion of each of nearby two raised field-oxide layers;
- a gate-dielectric layer being formed alternately over a plurality of semiconductor surfaces between said two stack-gate regions, said two stack-gate regions and their inner sidewalls, and said planarized thick-oxide layers;
- and
- a plurality of word lines being formed above the plurality of active regions and transversely to said elongated control-gate layers, wherein each of the plurality of word lines comprises a hard masking layer over a metal layer and a plurality of planarized conductive islands with each of the plurality of planarized conductive islands being formed over said gate dielectric layer between a pair of said two stack-gate regions.