Process to control etch profiles in dual-implanted silicon films
AssigneeKoninklijke Philips Electronics N.V.
InventorTammy Zheng
Life of this patent
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Abstract
A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack. Formation of micro-trenches, while achieving nearly vertical profiles, is substantially minimized. In a method for manufacturing a semiconductor device gate stack a breakthrough etch removes residual oxide and anti-reflection coating until the layer of amorphous silicon is exposed. A bulk etch removes the amorphous silicon until about 40% remains. The remaining amorphous silicon layer is etched with a high selectivity etch until oxide is exposed. Any residual poly or amorphous silicon is etched with a very high-selectivity ratio over etch until clear.
Claims13
A method for selectively etching a gate stack having a silicon layer covering a thin oxide layer which covers a substrate, the silicon layer having an anti-reflective coating layer thereon comprising:
- etching through the anti-reflective coating layer of the gate stack, with a first process gas having a fluorine-based chemistry, until the silicon layer is exposed;
- etching the silicon layer of the gate stack with a second process gas including a mixture of HBr, Cl2, and CF4;
- etching the gate stack with a third process gas including a mixture of HBr,Cl2 and 80% He—O2 until the thin oxide is exposed;
- and
- over etching the gate stack with a fourth process gas including a mixture of HBr, 80% He—O2 and He.
A method for etching unmasked areas of a gate stack having an anti reflective coating layer formed on a doped silicon layer on a silicon oxide on a substrate, comprising:
- placing the substrate into an etch chamber;
- etching the anti reflective coating layer with a breakthrough etch until the silicon layer is exposed;
- etching the silicon layer with a bulk etch until about 40% of the silicon layer remains;
- etching the remaining silicon layer with a high-selectivity etch including Cl2, HBr, and 80% He—O2 introduced into the etch chamber at flow rates in ranges of about 8-12 sccm, 120-180 sccm, and 12-18 sccm, respectively until the silicon oxide is exposed;
- and
- over-etching the remaining silicon layer with a very high-selectivity etch until silicon residues are cleared.
A method for etching unmasked areas of a gate stack having an anti reflective coating layer formed on a doped silicon layer on a silicon oxide on a substrate, comprising:
- placing the substrate into an etch chamber;
- etching the anti reflective coating layer with a breakthrough etch including CF4 introduced into, the etch chamber at a flow rate in the range of about 80 sccm to 120 sccm until the silicon layer is exposed;
- etching the silicon layer with a bulk etch including Cl2, HBr, and CF4 introduced into the etch chamber at flow rates in ranges of about 12-18 sccm, 70-110 sccm, and 9-15 sccm, respectively until about 40% of the silicon layer remains;
- etching the remaining silicon layer with a high-selectivity etch including Cl2, HBr, and 80% He—O2 introduced into the etch chamber at flow rates in ranges of about 8-12 sccm, 120-180 sccm, and 12-18 sccm, respectively until the silicon oxide is exposed;
- and
- over-etching the remaining silicon layer with a very high-selectivity etch including HBr, and 80% He—O2, and He introduced into the etch chamber at flow rates in ranges of about 160-240 sccm, 8-12 sccm, and 160-240 sccm, respectively until silicon residues are cleared.
Dependencies are inferred from the claim text.