Electro-mechanical polishing of platinum container structure

#The present invention relates to a method of electro-mechanical polishing (EMP) surfaces, especially surfaces of platinum container structures, during semiconductor device fabrication.

#As the dimensions of semiconductor devices continue to decrease, there is a need for high resolution patterning of device features. The need for smaller surface area for components, such as capacitors or transistors, along with the requirement to maintain high-reliability electrical connections, have led researchers to seek new materials and methods for fabricating semiconductor components.

#For example, promising candidates for materials for capacitor electrodes used in integrated circuits memory structures include noble metals, i.e., platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), rhodium (Rh), osmium (Os), silver (Ag) and gold (Au), as wells as their oxides, e.g., ruthenium oxide (RuO2), iridium oxide (IrO2) or osmium oxide (OsO2). The above-mentioned noble metals, of which platinum (Pt) is the most common, are all physically and chemically similar. They are either relatively stable metals or form conductive oxides. Their capacitance remains constant even when exposed to oxidizing or reducing atmospheres common to semiconductor fabrication. These metals are also resistant to hydrogen damage and do not affect the polarization of dielectric layers after annealing at high temperatures.

#The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments given below with reference to the accompanying drawings in which:

#FIG. 1 is an illustration of a DRAM CMOS gate structure, upon which a capacitor bottom electrode will be formed according to a method of the present invention;

#FIG. 2 is a partial view of the FIG. 1 structure at a stage of processing subsequent to that shown in FIG. 1;

#The present invention will be described as set forth in the preferred or exemplary embodiments of the detailed description and as illustrated in FIGS. 1-13. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural, logical, and electrical changes may be made without departing from the spirit or scope of the present invention.

#The term “substrate” used in the following description may include any semiconductor-based structure that has an exposed silicon surface. Structure must be understood to include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-germanium, germanium, or gallium arsenide. When reference is made to substrate in the following description, previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation.

#The term “noble metal” is intended to include not only elemental noble metals, i.e., platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), rhodium (Rh), osmium (Os), silver (Ag), gold (Au), and their oxides, but also noble metals with other trace metals or in various alloyed combinations with other metals as known in the semiconductor art, as long as such alloys retain the physical and chemical properties of the noble metal.