US 6,605,510 B2Granted

Semiconductor device with both memories and logic circuits and its manufacture

AssigneeFujitsu Limited

InventorHirofumi Watatani

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Abstract

A first MISFET is formed in a first active region on the surface of a semiconductor substrate. The drain region of the first MISFET has a lightly doped drain structure with a low concentration region and a high concentration region. The side wall spacer conformingly covers the side wall of the gate electrode and the surface of the low concentration region in the drain region. A second MISFET is formed in a second active region. The side wall spacer of the second MISFET covers the side wall of the gate electrode and extends to the surface of the source and drain regions. An interlayer insulating film covers the said first MISFET and second MISFET and is made of material having an etching resistance different from that of the side wall spacers of the first MISFET and second MISFET.

Claims9

Dependent claims

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming an element separation insulating film on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film;
(b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode;
(c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask;
(d) covering the first gate lamination structure with a first film made of insulating material;
(e) forming a second film on the first film, the second film being made of insulating material having an etching resistance different from an etching resistance of the first film;
(f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films;
(g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask;
(h) selectively removing the second film of the two layers constituting the first side wall spacer;
(i) forming metal silicide films on surfaces of regions where the impurities were implanted by said implanting step (g);
and
(j) forming an interlayer insulating film covering the first gate lamination structure and the metal silicide films.

8 more elements

A method of manufacturing a semiconductor device, comprising steps of:

(a) forming an element separation insulating film made of silicon oxide on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film;
(b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode;
(c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask;
(d) covering the first gate lamination structure with a first film made of insulating material having an etching resistance different from an etching resistance of silicon oxide;
(e) forming a second film made of silicon oxide on the first film;
(f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films;
(g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask;
(h) selectively removing the second film of the two layers constituting the first side wall spacer;
(i) forming a metal silicide film on surfaces of regions where the impurities were implanted by said second impurity implanting step;
and
(j) forming an interlayer insulating film covering the first gate lamination structure and metal silicide films.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/162,580Filed 6 Jun 2002 · division
Priority: JP 2000-562011 Mar 2000
Published: US 2002/0185662 A112 Dec 2002
Granted: 12 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10D 84/0147
The components including insulated gates, e.g. IGFETs: manufacturing their gate sidewall spacers
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs