US 6,605,501 B1 · Method of fabricating CMOS device with dual gate electrode

Abstract

A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar. The thinner first preliminary gate oxide is removed from over the first pillar and the thicker second preliminary gate oxide is thinned from over the second pillar. First final gate oxide is formed over the first pillar and second final gate oxide is formed on the second pillar. The second final gate oxide including the thinned second preliminary gate oxide. The second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.

Claims36

Dependent claims

A method of fabricating dual gate oxide thicknesses, comprising the steps of:

providing a substrate having a first pillar and a second pillar;
the first and second pillars each having side walls;
forming a gate dielectric layer over the substrate, the first and second pillars and the side walls of the first and second pillars;
forming first and second thin spacers over the gate dielectric layer covered side walls of the first and second pillars, respectively;
masking the second pillar leaving the first pillar unmasked;
removing the first thin spacers from the unmasked first pillar;
removing the mask from the masked second pillar;
oxidizing the structure to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar;
the second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar;
removing the thinner first preliminary gate oxide from over the first pillar and thinning the thicker second preliminary gate oxide from over the second pillar;
and
forming first final gate oxide over the first pillar and second final gate oxide on the second pillar;
the second final gate oxide including the thinned second preliminary gate oxide;
the second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.

11 more elements

A method of fabricating dual gate oxide thicknesses, comprising the steps of:

providing a substrate having a first pillar and a second pillar;
the first and second pillars having respective capping layers thereover and respective side walls;
forming a gate dielectric layer over the substrate, the first and second pillars and the side walls of the first and second pillars;
forming first and second thin spacers over the gate dielectric layer covered side walls of the first and second pillars, respectively;
masking the second pillar leaving the first pillar unmasked;
removing the first thin spacers from the unmasked first pillar;
removing the mask from the masked second pillar;
oxidizing the structure to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar;
the second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar;
removing the thinner first preliminary gate oxide from over the first pillar and thinning the thicker second preliminary gate oxide from over the second pillar;
and
forming first final gate oxide over the first pillar and second final gate oxide on the second pillar;
the second final gate oxide including the thinned second preliminary gate oxide;
the second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.

11 more elements

A method of fabricating dual gate oxide thicknesses, comprising the steps of:

providing a substrate having a first pillar and a second pillar;
the first and second pillars having respective capping layers thereover and respective side walls;
the capping layers being comprised of a material selected from the group consisting of nitride, silicon nitride, oxide, a nitride/oxide stack and a silicon nitride/oxide stack;
forming a gate dielectric layer over the substrate, the first and second pillars and the side walls of the first and second pillars;
forming first and second thin spacers over the gate dielectric layer covered side walls of the first and second pillars, respectively;
masking the second pillar leaving the first pillar unmasked;
removing the first thin spacers from the unmasked first pillar;
removing the mask from the masked second pillar;
oxidizing the structure to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar;
the second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar;
removing the thinner first preliminary gate oxide from over the first pillar and thinning the thicker second preliminary gate oxide from over the second pillar;
and
forming first final gate oxide over the first pillar and second final gate oxide on the second pillar;
the second final gate oxide including the thinned second preliminary gate oxide;
the second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.

12 more elements

Dependencies are inferred from the claim text.

Method of fabricating CMOS device with dual gate electrode

Life of this patent

Method of fabricating CMOS device with dual gate electrode

Life of this patent

Abstract

Claims36